Hybrid ASIC Design & Verification Intern

Hewlett Packard Enterprise Development LP; Roseville (CA); Hybrid; USD 48,000 - 56,000; Full time

Benefits offered by this job

Hybrid work arrangement

Health & wellbeing benefits

Career development programs

Job summary

Hewlett Packard Enterprise is seeking an ASIC Verification/Design Engineering Intern to join the Aruba ASIC development team. The internship offers a summer project contributing to current or future ASICs and learning from senior ASIC/VLSI engineers.

Responsibilities include RTL/Pre-Silicon and post-silicon verification, Formal Verification, script/tool development, and project scheduling. Students must be in a 4-year program and nearing degree completion (Dec 2027/May 2028).

Qualifications

• Currently enrolled in a 4-year University pursuing a degree in Computer Engineering, CS, or EE.
• At least 3rd Year of engineering courses completed (Dec 2027 or May 2028 degree).
• Experience with scripting languages (Python, PERL, TCL or equivalent).
• Experience with hardware design and Verilog.
• Experience with software programming languages (C/C++).
• Experience with AI tools and a passion for learning.
• Excellent communication and interpersonal skills.

Responsibilities

• RTL/Physical Design, Pre-Silicon verification.
• Post-silicon verification; Formal Verification.
• Script & Tool development; schedule breakdowns, document generation; other duties as assigned.

Skills

Python

PERL

TCL

Hardware design

C/C++

Verilog

AI tools

Communication

Problem solving

Time management

Collaboration

Education

4-year university pursuing degree in Computer/ Electrical Engineering or Computer Science

Tools

RTL/Physical Design tools

Job description

Hewlett Packard Enterprise is seeking an ASIC Verification/Design Engineering Intern to join the Aruba ASIC development team. The internship offers a summer project contributing to current or future ASICs and learning from senior ASIC/VLSI engineers.

Responsibilities include RTL/Pre-Silicon and post-silicon verification, Formal Verification, script/tool development, and project scheduling. Students must be in a 4-year program and nearing degree completion (Dec 2027/May 2028).