Hybrid ASIC Verification/Design Intern

HPE Aruba Networking; Roseville (CA); Hybride; USD 48 000 - 56 000; Plein temps

Résumé du poste

HPE Aruba Networking in California is seeking a university intern to work with the ASIC development team on next-generation networking chips. The internship includes hands-on RTL/Physical Design and verification tasks. You will learn from senior engineers and contribute to the team’s efforts in a fast-paced setting.

As an intern, you will engage in pre- and post-silicon verification, scripting and tool development, and collaborate across disciplines to meet project milestones.

Qualifications

• Must be currently enrolled in a 4-year University/College pursuing a degree in Computer Engineering, Computer Science, Electrical Engineering or equivalent.
• At least 3rd Year of engineering courses completed (December 2027 or May 2028 degree completion).

Responsabilités

• RTL/Physical Design, Pre-Silicon verification; post-silicon verification; Formal Verification; Script & Tool development; schedule breakdowns, document generation, and several other possible duties.

Connaissances

Python

Perl

Tcl

C

C++

Verilog

AI tools

Communication

Problem solving

Time management

Teamwork

Formation

Pursuing a B.S. in Computer Engineering/CS/EE

Outils

N/A

Description du poste

HPE Aruba Networking in California is seeking a university intern to work with the ASIC development team on next-generation networking chips. The internship includes hands-on RTL/Physical Design and verification tasks. You will learn from senior engineers and contribute to the team’s efforts in a fast-paced setting.

As an intern, you will engage in pre- and post-silicon verification, scripting and tool development, and collaborate across disciplines to meet project milestones.