Hybrid ASIC Clocks Verification Engineer (Equity)

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 116,000 - 190,000; Full time

Job summary

NVIDIA Corporation in Santa Clara, CA seeks an ASIC Clocks Verification Engineer to verify high-frequency clock structures and collaborate with design, verification and software teams. You’ll use SystemVerilog/UVM and Python/Perl to optimize clock flows for GPU chips.

Requires a Master’s in Electrical Engineering or equivalent and strong coding skills. Hybrid role with competitive salary, equity and benefits.

Qualifications

• Master’s degree in Electrical Engineering or equivalent experience.
• Experience with SystemVerilog and UVM.
• Experience with Design Verification, Logic Design, and Logic Synthesis.
• Strong coding in Python, Perl, or other scripting languages.

Responsibilities

• Verify high-frequency clock structures in collaboration with architects and ASIC designers.
• Support verification with SOC timing, DFT and lab triage of silicon bugs.
• Use Perl and Python to improve clocking workflow and efficiency.
• Collaborate with software and product groups to debug clock silicon issues.

Skills

SystemVerilog

UVM

Design Verification

Logic Design

Logic Synthesis

Python

Perl

Education

Master’s degree in Electrical Engineering

Job description

NVIDIA Corporation in Santa Clara, CA seeks an ASIC Clocks Verification Engineer to verify high-frequency clock structures and collaborate with design, verification and software teams. You’ll use SystemVerilog/UVM and Python/Perl to optimize clock flows for GPU chips.

Requires a Master’s in Electrical Engineering or equivalent and strong coding skills. Hybrid role with competitive salary, equity and benefits.