ASIC Clocks Verification Engineer – New College Grad 2026

Anysilicon; Santa Clara (CA); Hybrid; USD 140,000 - 190,000; Full time

Job summary

NVIDIA is seeking an exceptional ASIC Clocks Verification Engineer to join its GPU clocks group in Santa Clara, CA. You will verify high‑frequency clock structures and collaborate with architects, ASIC designers, and verification engineers to meet architectural constraints.

You will use SystemVerilog/UVM, Python, and Perl across teams, delivering clock data to SOC verification, timing, and DFT groups while addressing sub‑micron design challenges and debugging GPU clock silicon issues.

Qualifications

• Master’s degree in Electrical Engineering or equivalent experience.
• Practical experience with SystemVerilog and UVM.
• Experience in Design Verification, Logic Design, and Logic Synthesis.

Responsibilities

• Collaborate with architects, ASIC designers, and verification engineers to verify high-frequency clock structures.
• Engage with multiple teams to design GPU clock structures that meet architectural constraints.
• Utilize general verification principles to verify clock designs.
• Deliver clock information to SOC verification, timing, and DFT teams.
• Use Perl to enhance productivity across teams.
• Work with software and product groups to debug GPU clock silicon bugs.
• Design clocking structures to address sub-micron design challenges.
• Identify and propose improvements to enhance efficiency in GPU clocking design.

Skills

Python

Perl

Collaboration

Education

Master's degree in Electrical Engineering

Job description

NVIDIA is seeking an exceptional ASIC Clocks Verification Engineer to join its GPU clocks group, which is responsible for all aspects of GPU clocking. The role involves collaboration with various teams to ensure the design and verification of high-frequency clock structures, contributing to the evolution of modern AI and computing.

Responsibilities:

• Collaborate with architects, ASIC designers, and verification engineers to verify high-frequency clock structures.
• Engage with multiple teams to design GPU clock structures that meet architectural constraints.
• Utilize general verification principles to verify clock designs.
• Deliver clock information to SOC verification, timing, and DFT teams.
• Use Perl to enhance productivity across teams.
• Work with software and product groups to debug GPU clock silicon bugs.
• Design clocking structures to address sub-micron design challenges.
• Identify and propose improvements to enhance efficiency in GPU clocking design.

Qualifications:

• Master’s degree in Electrical Engineering or equivalent experience.
• Practical experience with SystemVerilog and Universal Verification Method (UVM).
• Experience in Design Verification, Logic Design, and Logic Synthesis.

Skills:

• Strong coding skills in Python, Perl, or other industry-standard scripting languages.
• Ability to collaborate effectively with cross-functional teams.