High-Speed Interface Pathfinding Hardware Engineer

Micron; Boise (ID); On-site; USD 180,000 - 240,000; Full time

Job summary

Micron Technology in Boise, Idaho, seeks an Interface Pathfinding Hardware Development Engineer to own the characterization plan for a high-speed test-chip program. You will design the bench, manage the measurement-uncertainty budget, and produce correlation reports with SI and digital teams.

The role drives automation, test-access, and AI-enabled workflows across timing, power delivery, and environmental corners, leading silicon bring-up and tape-out readiness.

Qualifications

• Advanced degree or equivalent experience in semiconductor characterization/test engineering.
• Expertise in high-speed time-domain measurement and jitter analysis.
• Experience with characterization plans, test-access/observability, and bench automation.

Responsibilities

• Derive characterization plans from architecture specs and SI budgets.
• Write register maps with observability/test-access requirements before RTL freeze.
• Develop and own the characterization hardware and automated data acquisition framework.
• Measure, calibrate, and de-embed to isolate device performance from noise.
• Lead silicon-to-model correlation and debug when deviations occur.
• Sign-off on tape-out readiness and generate post-silicon characterization reports.

Skills

High-speed timing

Pattern generator / analyzer

Automation & tooling

Characterization planning

DOE / design of experiments

Measurement uncertainty

AI-enabled workflows

Education

MSEE with 10+ years

BSEE with 12+ years

Tools

VNA S-parameters

Pattern generator

Measurement automation tools

Job description

Micron Technology in Boise, Idaho, seeks an Interface Pathfinding Hardware Development Engineer to own the characterization plan for a high-speed test-chip program. You will design the bench, manage the measurement-uncertainty budget, and produce correlation reports with SI and digital teams.

The role drives automation, test-access, and AI-enabled workflows across timing, power delivery, and environmental corners, leading silicon bring-up and tape-out readiness.