Interface Pathfinding Hardware Engineer — Characterization & AI

Micron Technology, Inc.; Boise, Northern (ID, KY); Hybrid; USD 150,000 - 210,000; Full time

Job summary

Micron Technology, Inc. is hiring an Interface Pathfinding Hardware Development Engineer to own characterization for a high-speed interface test-chip program.

You will plan tests, build automation, and produce correlation reports linking silicon to models, while collaborating with analog, digital, and SI teams. You’ll drive bench development, uncertainty budgets, and tape-out readiness with a senior, cross-disciplinary group, shaping next-gen interface technology and AI-enabled engineering

Qualifications

• Advanced degree or equivalent experience in semiconductor characterization or test engineering.
• Experience leading characterization programs from plan to sign-off.
• Strong knowledge of high-speed measurement and SI/link budget concepts.
• Familiarity with CI/CD style automation and data analytics for test data.

Responsibilities

• Derive the electrical characterization plan from architecture specs and SI link budget.
• Design observability and test-access requirements into the register map.
• Develop and own the automated data acquisition framework.
• Measure, calibrate, and de-embed characterization hardware to isolate noise.
• Lead cross-functional correlation and post-silicon reporting.
• Define bench capability and mentor junior engineers.
• Architect AI-assisted development and characterization pipelines.

Skills

High-speed measurement

Jitter transfer analysis

Pattern generator/analyzer

Design of Experiments

Automation & scripting

Characterization planning

PDN/load transient measurement

Test bench development

Silicon characterization

AI-enabled workflow

Education

MSEE

BS EE

Tools

VNA S-parameters

Test automation hardware

Pattern generator

Job description

Micron Technology, Inc. is hiring an Interface Pathfinding Hardware Development Engineer to own characterization for a high-speed interface test-chip program.

You will plan tests, build automation, and produce correlation reports linking silicon to models, while collaborating with analog, digital, and SI teams. You’ll drive bench development, uncertainty budgets, and tape-out readiness with a senior, cross-disciplinary group, shaping next-gen interface technology and AI-enabled engineering