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Avicena in Sunnyvale is seeking a package integration and SI/PI engineer to own the boundary between our ASIC and its package. You will ensure high-speed signals, clocks and power reach the chip cleanly, and that package constraints are reflected in the chip design early.
You will define die-package interfaces, perform signal and power integrity analyses across die, package and board, build models, run co-simulations, and collaborate with the core chip and package teams.
Avicena in Sunnyvale is seeking a package integration and SI/PI engineer to own the boundary between our ASIC and its package. You will ensure high-speed signals, clocks and power reach the chip cleanly, and that package constraints are reflected in the chip design early.
You will define die-package interfaces, perform signal and power integrity analyses across die, package and board, build models, run co-simulations, and collaborate with the core chip and package teams.