Package Integration & SI/PI Engineer for High-Speed Optics

Avicena Tech; Sunnyvale (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Avicena Tech in Sunnyvale, CA is seeking a Package Integration and SI/PI Engineer to own the boundary between the ASIC and its package. You will ensure high-speed signals, clocks and power reach the chip cleanly and translate package constraints into the chip design early.

You will run die-package co-simulation, exchange power and package models, and collaborate with the package and chip teams to optimize signal integrity and power integrity across die, package and board.

Qualifications

• MS in Electrical Engineering or BS with equivalent experience.

Responsibilities

• Own the die-package boundary for the ASIC: bump and pad map inputs, and signal and power assignment with the package team.
• Perform signal integrity analysis of high-speed and clock paths across die, package and board: channel extraction, crosstalk and return paths.
• Perform power integrity analysis from die through package to board: impedance targets, supply noise and ripple, and on-die and package decoupling.
• Build and exchange chip power and package models, and run die-package co-simulation with the chip team.
• Provide power maps for thermal analysis.
• Define ESD and supply strategy with the core analog and layout teams.
• Run die/package feasibility reviews and correlate models with lab measurements.

Skills

SI/PI experience

High-speed ICs and packages

S-parameters & TDR

Education

MS in Electrical Engineering

BS with equivalent experience

Tools

Ansys HFSS

SIwave

RedHawk

Cadence Sigrity and Clarity

Keysight ADS

Job description

Avicena Tech in Sunnyvale, CA is seeking a Package Integration and SI/PI Engineer to own the boundary between the ASIC and its package. You will ensure high-speed signals, clocks and power reach the chip cleanly and translate package constraints into the chip design early.

You will run die-package co-simulation, exchange power and package models, and collaborate with the package and chip teams to optimize signal integrity and power integrity across die, package and board.