Digital Design Engineer

QUALCOMM, Inc.; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks an ASIC front end design engineer for its high-speed parallel interfaces team.

You will design RTL and implement digital IPs for SoC-to-DRAM interfaces and multi-die links, collaborating with architecture, verification, timing, and physical design engineers to deliver high-performance, reliable interfaces. The role requires SystemVerilog expertise, gate‑level simulation, low‑power techniques, and experience with front end tool flows and silicon bring‑up in a

Qualifications

• Bachelor’s degree in Science, Engineering, or related field.
• Minimum 4 years ASIC design, verification, or related work experience.
• Hands-on experience with SystemVerilog and ASIC front end tool flows.
• Experience with high-speed parallel interfaces and low-power design.
• Design for test flows and silicon bring-up experience.

Responsibilities

• Design RTL and implement digital IPs for SoC interfaces.
• Collaborate with architecture, timing, verification and physical design teams.
• Develop and debug gate-level simulations; optimize power and timing.

Skills

SystemVerilog

RTL design

ASIC front end design

Low power design

Clock domain crossing

Education

Bachelor’s Degree in Science, Engineering, or related field

Master’s degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Job description

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm’s high speed parallel interfaces team is looking for a motivated and driven ASIC front end design engineer to work with a world class global team tasked to architect, design, and implement industry leading DDR and die-2-die interfaces fueling the company’s growth in high-speed compute, and server domains.

The Digital Design Engineer will be responsible for designing, developing RTL, and implementing digital IPs serving the systems that connect SoC to DRAM devices and provide reliable high-speed link in multi-die systems. In this existing role you will work closely with systems architecture, verification, timing, and physical design engineers to design and implement control and data-path blocks for SoC interfaces. Ideal candidate will have experience on high speed, low power digital logic design development with hands on experience on ASIC front end implementation tool flow methodologies and silicon bring up.

Expertise required on digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices and analysis, low power implementation and sign off, and gate level simulation debug.

Position requires working closely with cross functional teams to enable all phases of implementation and Si bring up. Prior experience with high-speed parallel physical interfaces designs and low power designs is a plus.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Required For This Role

• Bachelor’s Degree in Science, Engineering, or related field.
• Minimum 4 years ASIC design, verification, or related work experience.

Preferred Qualifications

• BS with 4 years or MS with 2 years relevant work experience
• Ideal candidate will have experience on high speed, low power digital logic design with hands on experience on ASIC front end implementation tool flows and silicon bring up.
• Expertise required on digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices and analysis, low power implementation and sign off, design for test (DFT) flows for stuck and TDF modes, gate level simulation bring up and debug.
• Position requires working closely with cross functional teams in high paced and dynamic environment to enable all phases of implementation and Si bring up.
• Prior experience with high-speed parallel physical interfaces designs and low power designs is a plus.

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EEO Employer

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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Pay Range And Other Compensation & Benefits

$121,800.00 - $182,600.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.