Head of Physical Design for 3D AI Accelerators

Acceler8 Talent; San Francisco (CA); On-site; USD 300,000 - 460,000; Full time

Job summary

Acceler8 Talent partners with a startup to hire a Director of Physical Design. You will lead full-chip PD for AI accelerators, driving netlist-to-GDSII signoff and coordinating with architecture, RTL, DFT, packaging, and foundry teams.

You will set PD methodology, flow development, and execute trade-offs across power, performance, area, and schedule in a fast-paced startup environment, ensuring scalable, high-quality tapeouts.

Qualifications

• 15–20 years of ASIC/SoC Physical Design experience with multiple silicon tapeouts.
• Degree in Electrical Engineering or related field (B.E./M.S.).
• Expert PD tools, flows, and process nodes (3nm/5nm/7nm).
• Strong leadership, communication, and project management skills.
• Experience with 3D-memory integration and complex subsystems.

Responsibilities

• Lead full-chip physical design from netlist to GDSII signoff.
• Own floorplanning, CTS, routing, timing closure, PD verification.
• Guide team, external partners, and tapeout readiness.
• Collaborate with SoC, DFT, packaging and foundry teams on integration.
• Develop power grid strategies and IR drop/EM analysis.
• Implement scan chain routing and test-mode constraints with DFT Lead.
• Ensure clean tapeouts and signoff across design blocks.

Skills

Leadership

Project management

PD tools/flows

NoC/Fabric/AXI interconnect

3D-memory integration

Tapeouts

Power integrity

DFT-aware PD

Effective communication

Education

B.E./M.S. in Electrical Engineering, VLSI or related

Tools

Innovus/Genus

Cadence Voltus

ANSYS RedHawk

Mentor Calibre / IC Validator

Job description

Acceler8 Talent partners with a startup to hire a Director of Physical Design. You will lead full-chip PD for AI accelerators, driving netlist-to-GDSII signoff and coordinating with architecture, RTL, DFT, packaging, and foundry teams.

You will set PD methodology, flow development, and execute trade-offs across power, performance, area, and schedule in a fast-paced startup environment, ensuring scalable, high-quality tapeouts.