Senior Physical Design Engineer for AI Accelerator

Acceler8 Talent; Palo Alto (CA); Sur place; USD 180 000 - 260 000; Plein temps

Résumé du poste

Acceler8 Talent is seeking an experienced Physical Design Engineer in Palo Alto to help develop a next‑generation AI ASIC designed for large language model inference. This hands‑on role covers physical implementation, floorplanning, timing closure, and tapeout readiness, collaborating closely with RTL, architecture, and implementation teams to meet stringent physical constraints and performance targets.

You will work with internal and external partners to drive PPA optimization, fix design

Qualifications

• Hands‑on experience with digital ASIC physical design and backend implementation.
• Ability to own meaningful physical implementation work on complex ASICs/SoCs.
• Strong floorplanning, placement, and timing constraints expertise.
• Experience optimizing PPA across the implementation process.
• Proven ability to investigate and resolve design closure issues.
• Collaboration with RTL, architecture, and backend teams.

Responsabilités

• Contribute to floorplanning and physical implementation of complex ASIC designs.
• Analyze and optimize power, performance, and area trade-offs.
• Identify constraints requiring RTL or architectural changes.
• Resolve physical design issues across floorplanning, timing, power, and design closure.
• Coordinate with RTL and microarchitecture to align front‑end and back‑end decisions.
• Collaborate with internal teams and external partners for handoffs.
• Support physical verification, implementation signoff, and tapeout readiness.
• Track outstanding issues and drive solutions to closure.

Connaissances

ASIC physical design

Backend implementation

Floorplanning

Timing constraints

Power optimization

RTL/microarchitecture collaboration

Design debugging

Senior‑level judgment

Description du poste

Acceler8 Talent is seeking an experienced Physical Design Engineer in Palo Alto to help develop a next‑generation AI ASIC designed for large language model inference. This hands‑on role covers physical implementation, floorplanning, timing closure, and tapeout readiness, collaborating closely with RTL, architecture, and implementation teams to meet stringent physical constraints and performance targets.

You will work with internal and external partners to drive PPA optimization, fix design