Director of Physical Design

Acceler8 Talent; San Francisco (CA); On-site; USD 300,000 - 460,000; Full time

Job summary

Acceler8 Talent partners with a startup to hire a Director of Physical Design. You will lead full-chip PD for AI accelerators, driving netlist-to-GDSII signoff and coordinating with architecture, RTL, DFT, packaging, and foundry teams.

You will set PD methodology, flow development, and execute trade-offs across power, performance, area, and schedule in a fast-paced startup environment, ensuring scalable, high-quality tapeouts.

Qualifications

• 15–20 years of ASIC/SoC Physical Design experience with multiple silicon tapeouts.
• Degree in Electrical Engineering or related field (B.E./M.S.).
• Expert PD tools, flows, and process nodes (3nm/5nm/7nm).
• Strong leadership, communication, and project management skills.
• Experience with 3D-memory integration and complex subsystems.

Responsibilities

• Lead full-chip physical design from netlist to GDSII signoff.
• Own floorplanning, CTS, routing, timing closure, PD verification.
• Guide team, external partners, and tapeout readiness.
• Collaborate with SoC, DFT, packaging and foundry teams on integration.
• Develop power grid strategies and IR drop/EM analysis.
• Implement scan chain routing and test-mode constraints with DFT Lead.
• Ensure clean tapeouts and signoff across design blocks.

Skills

Leadership

Project management

PD tools/flows

NoC/Fabric/AXI interconnect

3D-memory integration

Tapeouts

Power integrity

DFT-aware PD

Effective communication

Education

B.E./M.S. in Electrical Engineering, VLSI or related

Tools

Innovus/Genus

Cadence Voltus

ANSYS RedHawk

Mentor Calibre / IC Validator

Job description

Director of Physical Design

Acceler8 Talent is partnering with a startup designing a cutting-edge 3D-memory-integrated AI accelerator platform to hire an experienced, visionary Director of Physical Design.

In this role, you'd lead full-chip and complex subsystem physical design. This high-impact technical leadership role drives the physical design team from netlist ingestion through GDSII signoff, working closely with architecture, RTL design, DFT, packaging and foundry teams. As the primary technical authority for physical design methodology, flow development and execution, you'll make sound VLSI trade-off decisions across power, performance, area, schedule and design quality in a fast-paced startup environment.

What You'll Do:

• Lead full-chip physical design from netlist to GDSII signoff for complex AI accelerators, ensuring PPA and schedule goals. Drive physical design for 3D-Memory PHY Hard-IP development.
• Own floorplanning, CTS, routing, timing closure and physical verification, using industry standard tools and developing PD flows for Innovus/Genus.
• Drive team and work planning, external Design Service partners, resource allocation and milestone/quality/readiness reviews to ensure successful and timely tapeouts.
• Collaborate with SoC, DFT, Packaging, and Foundry teams to solve complex integration challenges, including 3D-memory/chiplet connectivity and power integrity.
• Develop and review power grid strategies for the compute die and 3D-memory interface; perform IR drop and electromigration (EM) analysis using Cadence Voltus or ANSYS RedHawk; account for TSV-based power delivery constraints.
• Implement scan chain routing, BIST controller placement, JTAG and boundary scan cell integration and test-mode power domain constraints in close coordination with the DFT Lead team.
• Own DRC/LVS/ERC signoff using Mentor Calibre or IC Validator; drive clean tapeout across all design blocks.

What You Bring:

• B.E./M.S. in Electrical Engineering, VLSI or a related discipline
• 15–20 years experience in ASIC/SoC Physical Design with a proven track record of successful silicon tapeouts.
• Expert-level proficiency in PD tools, flows and advanced process nodes (3nm/5nm/7nm).
• Mastery of CTS, timing/congestion‑aware routing, SI‑aware signoff and low‑power/DFT design flows.
• Experience with NoC/Fabric/AXI interconnect physical implementation; placement and routing of high‑performance on‑chip networks.
• Experience with DFT‑aware physical design; scan chain routing, BIST controller placement, JTAG/boundary scan integration and test‑mode physical constraints.
• Experience with low‑power physical implementation; UPF‑based multi‑voltage domains, power gating, retention flop placement, level shifters and isolation cells.
• Strong leadership, communication, and project management skills in fast‑paced environments.
• Proven track record of multiple successful SoC productizations; from physical design through post‑silicon qualification and production release.