Head of Analog & LPDDR PHY Design (High-Speed)

AMD; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD seeks a leader to manage the Memory I/O design team, defining circuit architecture and implementing high-speed LPDDR PHY blocks. You will collaborate across Analog, Digital, Firmware, and Verification to ensure feature-rich, efficient designs and robust simulations.

The ideal candidate has 5+ years of management experience guiding multiple IPs from concept to production, with strong communication and risk-mitigation skills.

Qualifications

• Bachelor, Master, or PhD in computer or electrical engineering.
• Minimum 5+ years of team management experience.
• Proven track record leading multiple PHY design IPs from design to production.

Responsibilities

• Define circuit architecture for LPDDR PHYs and lead design implementation of low-power, area-efficient blocks.
• Collaborate with Analog Mixed Signal, Digital, Firmware and Verification teams to ensure optimal PHY architecture and feature coverage.
• Manage execution and deliverables across customers and stakeholders.
• Develop models for link-level statistical performance simulations and apply to design optimization.

Skills

Analytical thinking

Communication skills

Team leadership

RTL/FW debugging

IO/system integration

Education

Bachelors/Masters/PhD in Computer or Electrical Engineering

Tools

Verilog/AMS

MATLAB/Simulink

Job description

AMD seeks a leader to manage the Memory I/O design team, defining circuit architecture and implementing high-speed LPDDR PHY blocks. You will collaborate across Analog, Digital, Firmware, and Verification to ensure feature-rich, efficient designs and robust simulations.

The ideal candidate has 5+ years of management experience guiding multiple IPs from concept to production, with strong communication and risk-mitigation skills.