Senior Memory PHY Architect for High-Speed Interfaces

AMD; Santa Clara (CA); Presencial; USD 180 000 - 260 000; Tempo integral

Resumo da oferta

AMD is seeking a seasoned Memory PHY Design Engineer to shape digital PHY architecture, RTL, and firmware for LPDDR and DDR technologies. You will collaborate with analog, circuit, verification, firmware, physical design, and system teams to improve power, performance, and area across programs.

You will lead the Memory PHY digital architecture from concept to RTL, with responsibilities spanning synthesis, timing, and post‑silicon support.

Qualificações

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field preferred.
• Deep expertise in Memory PHY architecture and high‑speed I/O subsystems (LPDDR/DDR/HBM/SerDes).
• Proficiency in Verilog or SystemVerilog, and scripting (Python, Perl, Tcl).

Responsabilidades

• Define product features from architecture to technical specs and provide direction to execution teams.
• Lead Memory PHY digital architecture development from pathfinding through RTL implementation and physical realization.
• Architect and implement PHY link‑layer functionality with analog and system architects.
• Drive co‑design, digital logic, RTL coding, and firmware for high‑speed memory interfaces.
• Guide synthesis, timing analysis, and physical design to meet power, performance, and area targets.
• Collaborate across teams to define, implement, and validate new features.

Conhecimentos

Memory PHY architecture

Verilog/SystemVerilog

Python scripting

RTL design

Formação académica

Bachelor's in Electrical/Computer Engineering

Master’s or PhD preferred

Descrição da oferta de emprego

AMD is seeking a seasoned Memory PHY Design Engineer to shape digital PHY architecture, RTL, and firmware for LPDDR and DDR technologies. You will collaborate with analog, circuit, verification, firmware, physical design, and system teams to improve power, performance, and area across programs.

You will lead the Memory PHY digital architecture from concept to RTL, with responsibilities spanning synthesis, timing, and post‑silicon support.