Senior Manager, High-Speed Analog & Memory IP

Advanced Micro Devices, Inc.; Santa Clara (CA); Hybrid; USD 180,000 - 260,000; Full time

Benefits offered by this job

AMD benefits

Job summary

Advanced Micro Devices, Inc. (AMD) in Santa Clara, CA, seeks a senior candidate to lead the Memory I/O design team. You will define circuit architectures, specify high-speed blocks, calibrate and model link performance, and guide Analog, Digital and Firmware teams through to production.

The role emphasizes strong analytical thinking, risk management, and hands-on circuit design with an emphasis on low-power, area-efficient implementations. Visa sponsorship is not available.

Qualifications

• Degree in electrical/computer engineering or related field.
• Experience with high-speed IOs, LPDDR PHYs is preferred.
• Strong communication and leadership abilities.

Responsibilities

• Define circuit architecture and design implementations for LPDDR PHYs.
• Collaborate with Analog Mixed Signal, Digital Design and Firmware teams.
• Lead execution across IPs from design to production.
• Develop link-level performance models and simulations.
• Document micro-architecture and algorithm definitions.

Skills

PHY design

Circuit architecture

Signal integrity

RTL/FW analysis

Verilog/AMS

Team leadership

Modeling & simulation

Education

Bachelor's/Master's/PhD in Electrical/Computer Engineering

Tools

Matlab/Simulink

Verilog/AMS

SPICE

Job description

Advanced Micro Devices, Inc. (AMD) in Santa Clara, CA, seeks a senior candidate to lead the Memory I/O design team. You will define circuit architectures, specify high-speed blocks, calibrate and model link performance, and guide Analog, Digital and Firmware teams through to production.

The role emphasizes strong analytical thinking, risk management, and hands-on circuit design with an emphasis on low-power, area-efficient implementations. Visa sponsorship is not available.