Lead DFT/DFx Architecture & RTL for High-Speed PHYs

AMD; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD is seeking an experienced DFT/DFx Leader to support high-speed SerDes PHYs, Memory PHYs, and die-to-die interconnect IPs. You will own architecture, RTL implementation, and test methodology while collaborating across design, verification, and product engineering teams to deliver production-ready IP.

The role requires strong problem-solving skills, autonomy, and cross-functional leadership in a fast-paced SoC environment.

Qualifications

• BS/MS in Electrical/Computer Engineering or related field.
• Extensive RTL/DFT development experience.
• Experience with silicon bring-up and test processes.

Responsibilities

• Define DFT/DFx architecture and methodology for high-speed IPs.
• Implement DFT/DFx features in RTL using Verilog/SystemVerilog.
• Lead ATPG pattern generation, simulation, and debug.
• Collaborate with design, verification, CAD and test teams to deliver robust IP.

Skills

Verilog/SystemVerilog

RTL design

DFT/DFx

ATPG/DFT flows

JTAG/IJTAG

Scripting

Collaboration

Education

BS/MS in Electrical/Computer Engineering

Tools

Siemens Tessent

Synopsys VCS

Verdi

TestKompress

Job description

AMD is seeking an experienced DFT/DFx Leader to support high-speed SerDes PHYs, Memory PHYs, and die-to-die interconnect IPs. You will own architecture, RTL implementation, and test methodology while collaborating across design, verification, and product engineering teams to deliver production-ready IP.

The role requires strong problem-solving skills, autonomy, and cross-functional leadership in a fast-paced SoC environment.