Senior Manager - Analog Design

AMD; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD seeks a leader to manage the Memory I/O design team, defining circuit architecture and implementing high-speed LPDDR PHY blocks. You will collaborate across Analog, Digital, Firmware, and Verification to ensure feature-rich, efficient designs and robust simulations.

The ideal candidate has 5+ years of management experience guiding multiple IPs from concept to production, with strong communication and risk-mitigation skills.

Qualifications

• Bachelor, Master, or PhD in computer or electrical engineering.
• Minimum 5+ years of team management experience.
• Proven track record leading multiple PHY design IPs from design to production.

Responsibilities

• Define circuit architecture for LPDDR PHYs and lead design implementation of low-power, area-efficient blocks.
• Collaborate with Analog Mixed Signal, Digital, Firmware and Verification teams to ensure optimal PHY architecture and feature coverage.
• Manage execution and deliverables across customers and stakeholders.
• Develop models for link-level statistical performance simulations and apply to design optimization.

Skills

Analytical thinking

Communication skills

Team leadership

RTL/FW debugging

IO/system integration

Education

Bachelors/Masters/PhD in Computer or Electrical Engineering

Tools

Verilog/AMS

MATLAB/Simulink

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

The Role

AMD seeks a candidate who will be managing the Memory I/O design team supporting the definition, specification, system simulation and implementation of future LPDDR IPs. The focus of the activity will be centered around the circuit architecture and design of critical high-speed analog and digital blocks, definition of specifications for the high speed data path; definition of algorithms for calibration, equalization; and development of abstracted models for link performance simulations.

The Person

The ideal candidate will have analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation. You have Strong/effective communication skills and enthusiastic team-first mentality.

Key Responsibilities

• Manage and contribute to the definition of circuit architecture and to the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for LPDDR PHYs
• Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
• Manage execution and deliverables across customers and stakeholders
• Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design.
• Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the training and verification of the circuits.
• Participate and contribute to the definition of development flows that improve efficiency and quality of execution

Preferred Experience

• A proven track record of successfully leading execution of multiple PHY designs with very good Silicon results.
• A proven successful track record in circuit-architecture and modeling for High Speed IOs
• Solid and hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
• Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink) as well as Verilog/AMS-based.
• Good knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
• Ability to dig into RTL or FW code supporting the custom circuit implementation
• Minimum 5+ years of team management experience leading multiple IPs from design to production

Academic Credentials

• Bachelors, Masters or Ph.D. degree in computer engineering/Electrical Engineering.

LOCATION:

Santa Clara, CA

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.