Memory Systems Architect: LPDDR & DRAM-Buffer Leader

AMD; Georgia; Hybrid; USD 180,000 - 240,000; Full time

Job summary

AMD's Memory Standards Architecture team seeks a LPDDR and DRAM-Buffer Standards Architect to own the architecture strategy across generations and devices. The role requires deep LPDDR and DDR knowledge, leadership across internal teams, and influence with external partners to shape the memory ecosystem.

You will define roadmaps, represent AMD in JEDEC, and align DRAM vendors, suppliers, and platforms to deliver robust, power-aware, and interoperable solutions for client, server, and embedded

Qualifications

• Deep LPDDR and DDR knowledge with architecture experience.
• Experience with DRAM-bit architectures, buffers, and memory systems.
• Ability to influence across internal teams and external partners.

Responsibilities

• Own AMD’s LPDDR and DRAM-buffer architecture strategy across business units and product generations.
• Lead AMD technical positions for LPDDR devices and advanced DRAM buffers.
• Advance AMD positions in JEDEC through proposals, ballots, negotiations.
• Align AMD with DRAM vendors, buffer suppliers, and the memory ecosystem.
• Consolidate product, platform, design, validation, firmware, and system needs into unified AMD positions.
• Strategy and roadmap: Define multi-generation LPDDR and DRAM-buffer strategy.
• Standards leadership: Represent AMD in JEDEC and drive consensus.
• Device and buffer architecture: Define requirements for LPDDR devices and buffers.
• System integration: Coordinate DRAM and buffer architectures with controller, PHY, SoC, package, module, board, firmware, validation, and platform requirements.
• Implementation specifications: Deliver architecture, SPD, configuration, firmware, power, security requirements.
• Ecosystem readiness: Align DRAM vendors and suppliers on roadmaps and interoperability.
• Lead cross-functional architecture workgroups and provide reusable solutions and guidance.

Skills

LPDDR architecture

DRAM-buffer architectures

JEDEC standards

cross-functional leadership

system-level architecture

power and performance tradeoffs

collaboration with vendors

Education

Bachelor's degree in EE/CE/CS

Master's degree or PhD preferred

Job description

AMD's Memory Standards Architecture team seeks a LPDDR and DRAM-Buffer Standards Architect to own the architecture strategy across generations and devices. The role requires deep LPDDR and DDR knowledge, leadership across internal teams, and influence with external partners to shape the memory ecosystem.

You will define roadmaps, represent AMD in JEDEC, and align DRAM vendors, suppliers, and platforms to deliver robust, power-aware, and interoperable solutions for client, server, and embedded