HBM SoC Physical Design Intern for AI & HPC

Micron Technology; Folsom (AL); On-site; USD 54,000 - 69,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Equity

Job summary

Micron Technology seeks an SoC Physical Design Intern for the HBM team in the United States. You will support floorplanning, placement, clock tree synthesis, routing, and physical optimization while learning timing analysis and signoff methods.

The role emphasizes automation and scripting with Python, Tcl, and shell, plus collaboration across design teams. You will gain hands-on experience in AI-enabled design techniques, timing constraints, and multi‑corner analysis, contributing to next‑gen

Qualifications

• 0-2 years of relevant experience through internships, research, coursework, or academic projects in ASIC design, VLSI, digital IC design, computer architecture, or physical design.
• Currently pursuing a Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Knowledge of ASIC design flow concepts, including synthesis, place-and-route, static timing analysis, and physical verification.

Responsibilities

• Support the physical implementation of SoC design blocks, including floorplanning, placement, clock tree synthesis, routing, and physical optimization activities.
• Analyze timing, power, area, congestion, and physical verification results to find opportunities for design improvement and optimization.
• Assist with static timing analysis, timing closure, and debugging across multiple operating modes and process corners.
• Develop and enhance automation tools, scripts, reports, and workflows using Python, Tcl, shell scripting, and AI-assisted solutions.
• Collaborate with multi-functional engineering teams to document results, participate in design reviews, and present technical findings.

Skills

ASIC design concepts

Python scripting

Teamwork

Communication

AI-enabled tools

Education

Master's degree in Electrical Engineering

Tools

Cadence Innovus/Tempus

Synopsys ICC2/PrimeTime

Siemens Calibre

Job description

Micron Technology seeks an SoC Physical Design Intern for the HBM team in the United States. You will support floorplanning, placement, clock tree synthesis, routing, and physical optimization while learning timing analysis and signoff methods.

The role emphasizes automation and scripting with Python, Tcl, and shell, plus collaboration across design teams. You will gain hands-on experience in AI-enabled design techniques, timing constraints, and multi‑corner analysis, contributing to next‑gen