Intern: AI-Driven Digital Design & Automation (HBM PHY)

1000 Micron Technology, Inc.; Richardson (TX); On-site; USD 34,000 - 55,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time-off

Paid holidays

Job summary

Micron Technology, Inc. in Richardson, TX, seeks a Senior or Graduate Engineering Intern to assist HBM architecture with digital design methodologies, automation frameworks, timing analysis flows, and architecture validation for next-gen HBM PHY/IO subsystems.

You will gain hands-on experience in digital design, verification, automation, and timing analysis, including AI-assisted workflows using LLMs and Generative AI to boost productivity. Opportunity to work with cutting-edge memory tech.

Qualifications

• Currently pursuing a Master's or Ph.D. in Electrical/Computer Engineering or CS.
• Strong grasp of digital design concepts including FSMs, pipelining, CDC, timing analysis, and computer architecture.
• Experience with RTL design and verification using Verilog or SystemVerilog.
• Proficiency in Python, C++, or equivalent, and Linux-based development experience.
• Good analytical and communication skills.

Responsibilities

• Support digital design, integration, and timing analysis for HBM PHY/IO subsystems, including timing constraints and closure.
• Develop and verify using Verilog/SystemVerilog and UVM environments; analyze results and debug issues.
• Create Python-based automation tools and AI-assisted workflows to improve engineering efficiency.
• Collaborate with architecture, design, verification, and product teams to evaluate features and validate architectures.
• Document findings and present results in design reviews and discussions.

Skills

Verilog

SystemVerilog

Python

C++

Linux

Digital design

Education

Master's or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Cadence

Synopsys

Siemens

Job description

Micron Technology, Inc. in Richardson, TX, seeks a Senior or Graduate Engineering Intern to assist HBM architecture with digital design methodologies, automation frameworks, timing analysis flows, and architecture validation for next-gen HBM PHY/IO subsystems.

You will gain hands-on experience in digital design, verification, automation, and timing analysis, including AI-assisted workflows using LLMs and Generative AI to boost productivity. Opportunity to work with cutting-edge memory tech.