HBM Datapath Architect - Lead High-Speed Memory Design

Micron Technology, Inc; Folsom (CA); On-site; USD 146,000 - 297,000; Full time

Job summary

Micron Technology, Inc. is seeking a Staff Design Engineer in the HBM Architecture team to architect, design, and optimize high‑speed datapath circuits for next‑generation high bandwidth memory products.

This role collaborates across design, PHY, ECC, verification, layout, and system groups to deliver robust datapath designs from concept through silicon bring‑up. The candidate will drive datapath architectures for core and logic dies, focusing on bandwidth, power efficiency, reliability, and

Qualifications

• 7+ years of relevant industry experience or 5+ years with a Master’s degree.
• 3+ years of experience in high‑speed digital datapath design (memory, SerDes, or SoC datapath).
• 3+ years of hands‑on experience with digital schematic build, RTL, or mixed‑signal datapath implementations.

Responsibilities

• Architect and design HBM read and write datapath for core and logic die.
• Develop high‑speed datapath circuits for multi‑channel HBM architectures.
• Optimize datapath designs for bandwidth, power, area, and timing closure.
• Design and integrate data reliability features (parity, ECC hooks, lane redundancy).
• Collaborate with design, PHY, verification, and layout teams from concept to silicon bring‑up.
• Drive RTL‑level datapath implementations including clocking and reset strategies.
• Contribute to design reviews, documentation, and mentoring across HBM programs.
• Leverage AI tools to improve productivity and problem solving.

Skills

HBM datapath design

RTL design

Datapath architectures

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree (preferred)

Job description

Micron Technology, Inc. is seeking a Staff Design Engineer in the HBM Architecture team to architect, design, and optimize high‑speed datapath circuits for next‑generation high bandwidth memory products.

This role collaborates across design, PHY, ECC, verification, layout, and system groups to deliver robust datapath designs from concept through silicon bring‑up. The candidate will drive datapath architectures for core and logic dies, focusing on bandwidth, power efficiency, reliability, and