Senior HBM Datapath Architect — Equity & Impact

Energy Jobline ZR; Richardson (TX); On-site; USD 146,000 - 297,000; Full time

Job summary

Micron Technology's HBM Architecture team seeks an experienced engineer to design high-speed datapath blocks for next-generation memory products. You will own RTL-level implementation, from clocking and reset strategies to data paths across core and logic dies.

You will collaborate with PHY, DFT, verification, and layout teams, optimize for bandwidth, power, area, and timing, and contribute to design reviews, documentation, and mentorship. This is a full-time role based in the United States.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering, or related field, with 7+ years of experience or Master’s with 5+ years.
• 3+ years of experience in high-speed digital datapath design (memory, SerDes, or SoC datapath).
• 3+ years hands-on experience with digital schematic build, RTL, or mixed-signal datapath implementations.

Responsibilities

• Architect and design HBM read and write datapath across core and logic die, including alignment and timing.
• Develop high-speed datapath circuits for multi-channel HBM architectures and wide internal buses.
• Optimize datapath designs for bandwidth, power, area, and timing at advanced nodes.
• Design and integrate data reliability features, including parity, ECC hooks, lane redundancy, and remapping.
• Collaborate with multi-functional teams to translate specifications into robust micro-architectures.
• Drive schematic-level and RTL-level datapath implementations, including clocking, gating, and reset strategies.

Skills

High-speed datapath design

RTL design

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Master’s degree in Electrical/Computer Engineering or related field

Tools

Verilog/VHDL

STA tools

Job description

Micron Technology's HBM Architecture team seeks an experienced engineer to design high-speed datapath blocks for next-generation memory products. You will own RTL-level implementation, from clocking and reset strategies to data paths across core and logic dies.

You will collaborate with PHY, DFT, verification, and layout teams, optimize for bandwidth, power, area, and timing, and contribute to design reviews, documentation, and mentorship. This is a full-time role based in the United States.