HBM Memory Architect & Principal DRAM Design Lead

Micron

Garland (TX)

On-site

USD 150,000 - 210,000

Full time

14 days+
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Benefits offered by this job

Medical, dental & vision plans
Paid time off and holidays
Equal opportunity employer

Job summary

Micron Technology is seeking a Principal Design Engineer to architect and deliver high‑performance DRAM circuits for advanced technology nodes. You will lead circuit building, layout, verification and silicon validation, partnering with multiple teams to deliver scalable, manufacturable memory solutions.

You will influence performance, power, reliability and time‑to‑market while guiding reviews, documentation and best‑practice standards across design and layout groups.

Qualifications

  • BS in Electrical Engineering or related field with advanced CMOS/analog coursework.
  • Strong Cadence Virtuoso, physical layout and floorplanning experience.
  • Proven experience using FINESIM, HSPICE and VERILOG for circuit sims.
  • Ability to solve ambitious technical problems with design impact.
  • Deep knowledge of DRAM subsystem architecture and operation.

Responsibilities

  • Design and optimize DRAM circuits across digital, analog and memory cores.
  • Develop floorplans, routing, power networks, margins, timings and die-size tradeoffs.
  • Run advanced circuit simulations for speed, power, noise and reliability.
  • Model parasitics, verify power/signal integrity, support tape-outs.
  • Lead reviews and standardize best practices across design teams.
  • Coordinate layout and build resources and manage critical paths.

Skills

Electrical engineering fundamentals
Cadence Virtuoso
Physical layout
Circuit floorplanning
Finite element/analog SPICE tools

Education

Bachelor's degree in Electrical Engineering
MS or PhD in Electrical Engineering

Tools

FINESIM
HSPICE
VERILOG

Job description

Micron Technology is seeking a Principal Design Engineer to architect and deliver high‑performance DRAM circuits for advanced technology nodes. You will lead circuit building, layout, verification and silicon validation, partnering with multiple teams to deliver scalable, manufacturable memory solutions.

You will influence performance, power, reliability and time‑to‑market while guiding reviews, documentation and best‑practice standards across design and layout groups.

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