HBM Architecture Intern: AI/HPC Innovation and Benefits

Micron; Folsom (CA); On-site; USD 118,856,000 - 169,280,000; Full time

Benefits offered by this job

Medical, Dental, Vision plans

Paid time off

Paid holidays

Paid family leave

Job summary

Micron Technology's Memory Systems Architecture team seeks an intern to help shape future HBM products for AI and HPC workloads. You will work with senior architects to assess features, build models, and analyze trade-offs to improve memory performance and reliability.

Responsibilities include researching HBM architecture, developing performance models and tools in Python/C++, and collaborating with design and memory controller teams to define specifications and roadmaps.

Qualifications

• 0-2 years of relevant experience in computer architecture or memory systems.
• Pursuing Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science or related field.
• Experience with memory hierarchies, DRAM, interconnects, or hardware design.
• Programming in Python and C++, SystemVerilog or similar engineering languages.
• Ability to read technical specifications and datasheets.
• Strong analytical and communication skills.
• Experience using AI tools in engineering workflows.

Responsibilities

• Research and evaluate next-generation HBM architecture and microarchitecture features.
• Develop and enhance performance models, simulators, and analytical tools.
• Analyze workload behavior and provide recommendations for future development.
• Utilize AI-assisted engineering tools to accelerate software development and documentation.
• Collaborate with architecture, design, memory controller, and cross-functional teams.

Skills

Python

C++

SystemVerilog

Engineering languages

Education

Bachelor's degree

Master's degree

PhD

Tools

Ramulator

DRAMSim

gem5

Job description

Micron Technology's Memory Systems Architecture team seeks an intern to help shape future HBM products for AI and HPC workloads. You will work with senior architects to assess features, build models, and analyze trade-offs to improve memory performance and reliability.

Responsibilities include researching HBM architecture, developing performance models and tools in Python/C++, and collaborating with design and memory controller teams to define specifications and roadmaps.