HBM Architecture Intern for AI & HPC

Micron Technology; Folsom (CA); On-site; USD 104,000 - 106,000; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

Paid Time Off

Paid Holidays

Job summary

Micron Technology in California is seeking a Memory Systems Architecture Intern to contribute to the architecture and microarchitecture development of future High Bandwidth Memory products. You will work with experienced architects to evaluate features, analyze trade-offs, and develop performance models for AI and HPC workloads.

Collaborate with cross-functional teams including design, memory controller, and architecture to define features, participate in design reviews, and help roadmap

Qualifications

• 0-2 years of relevant experience in computer architecture, memory systems, or related fields.
• Pursuing a BS, MS, or PhD in a related field.
• Coursework or projects in computer architecture, memory hierarchies, DRAM technologies, or hardware design.
• Programming experience with Python and C++ or SystemVerilog.

Responsibilities

• Research and evaluate next-generation HBM architecture and microarchitecture features.
• Develop performance models, simulators, and analytical tools to assess trade-offs.
• Analyze workload behavior and provide recommendations for future HBM products.
• Utilize AI-assisted tools to accelerate engineering workflows and validate outputs.
• Collaborate with cross-functional teams for feature definition and roadmaps.

Skills

Python

C++

SystemVerilog

Education

Bachelor's or Master's in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Ramulator

DRAMSim

gem5

Job description

Micron Technology in California is seeking a Memory Systems Architecture Intern to contribute to the architecture and microarchitecture development of future High Bandwidth Memory products. You will work with experienced architects to evaluate features, analyze trade-offs, and develop performance models for AI and HPC workloads.

Collaborate with cross-functional teams including design, memory controller, and architecture to define features, participate in design reviews, and help roadmap