Hardware Engineering Manager: High-Speed IP & Tape-Out

Baya Systems; Santa Clara (CA); Presencial; USD 150.000 - 180.000; Jornada completa

Descripción de la vacante

Baya Systems, based in Santa Clara, CA, is seeking a Hardware Engineering Manager/Director to lead a talented team of engineers focused on high-speed interconnect. The successful candidate will manage the end-to-end execution of IP blocks, emphasizing silicon success through best practices in microarchitecture, RTL design, and verification.

Candidates should have over 8 years of experience in ASIC/IP development, a strong background in high-speed protocols such as PCIe and UCIe, and proficiency in SystemVerilog and Verilog. Join us and be a part of a fast-paced startup culture that fosters innovation.

Formación

• 8+ years of experience in ASIC/IP development, with at least 2-3 years in a leadership or management role.
• Strong background in high-speed protocols like PCIe, UCIe, and CXL.
• Deep understanding of modern verification methodologies and formal verification.

Responsabilidades

• Lead a team of RTL Microarchitects and Design Verification Engineers.
• Drive development from microarchitecture specs to RTL implementation.
• Oversee development of verification test plans and emulation platforms.
• Collaborate with cross-functional teams to balance power, performance, area, and timing.

Conocimientos

Leadership

High-speed protocols

SystemVerilog

Verilog

UVM

Agile project management

Educación

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field

Herramientas

EDA simulation/synthesis tools

Descripción del empleo

Baya Systems, based in Santa Clara, CA, is seeking a Hardware Engineering Manager/Director to lead a talented team of engineers focused on high-speed interconnect. The successful candidate will manage the end-to-end execution of IP blocks, emphasizing silicon success through best practices in microarchitecture, RTL design, and verification.

Candidates should have over 8 years of experience in ASIC/IP development, a strong background in high-speed protocols such as PCIe and UCIe, and proficiency in SystemVerilog and Verilog. Join us and be a part of a fast-paced startup culture that fosters innovation.