Manager/Director of Hardware Engineering

Baya Systems; Santa Clara (CA); Presencial; USD 220.000 - 320.000; Tempo integral

Benefícios oferecidos por esta vaga

Equity

Performance incentives

Onsite advantage at Santa Clara

Resumo da vaga

Baya Systems is seeking a Manager/Director of Hardware Engineering in Santa Clara, onsite only. You will lead a first-level team of RTL microarchitects and DV engineers, owning end-to-end interconnect IP from design to tape-out.

Requirements include 8+ years in ASIC/IP development with 2–3 years in leadership, strong SystemVerilog/Verilog skills, and expertise in high-speed protocols like PCIe/UCIe/CXL/Ethernet. A startup mindset and collaboration across disciplines are essential.

Qualificações

• Requires 8+ years in ASIC/IP development with leadership experience.
• Strong background in PCIe, UCIe, CXL, Ethernet, or SerDes.
• Proficiency in SystemVerilog/Verilog and industry-standard verification flows (UVM/OVM).
• Startup mindset with proven delivery in fast-paced environments.

Responsabilidades

• Lead and mentor a team of 8–12 RTL and DV engineers.
• Drive IP interconnect development from microarchitecture to tape-out.
• Oversee verification test plans, coverage, and emission of high-quality silicon blocks.
• Collaborate across architecture, physical design, and system teams to meet PPA targets.
• Establish metrics, methodologies, and agile practices to hit tape-out milestones.

Conhecimentos

Leadership

ASIC/IP development

High-speed protocols

SystemVerilog

Verilog

UVM/OVM

Constrained random testing

Formal verification

Coverage analysis

Formação

B.S./M.S. in Electrical or Computer Engineering

Descrição da vaga

Manager/Director of Hardware Engineering

Baya Systems is inspired by thebaya bird , also known as theweaver . Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.

Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!

Manager/Director of Hardware Engineering

Santa Clara, CA ( Onsite only)

Reports to: VP of Hardware Engineering

Role Overview

As a Hardware Engineering Manager, you will lead a talented, first-level team of RTL Microarchitects and Design Verification (DV) Engineers. Operating in a fast-paced IP interconnect startup environment, you will own the end-to-end execution of high-speed interconnect IP blocks. You will ensure first-pass silicon success by driving microarchitecture, RTL design, and rigorous verification methodologies.

What You’ll Do

• Team Leadership: Directly manage, mentor, and grow a team of 8-12 RTL and DV engineers.
• Execution & Delivery: Drive the development of high-speed interconnect IP from microarchitecture specifications to RTL implementation and tape-out.
• Verification Excellence: Oversee the development of robust, coverage-driven verification test plans, UVM/OVM environments, and emulation platforms.
• Cross-Functional Collaboration: Work closely with architecture, physical design, and system teams to balance power, performance, area (PPA), and timing requirements.
• Process Optimization: Define and establish engineering metrics, standard methodologies, and agile project management tools to meet strict tape-out milestones.

Requirements & Qualifications

• Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 8+ years of industry experience in ASIC/IP development, with at least 2-3 years in a technical leadership or management role.
• Technical Domain: Strong background in high-speed protocols (e.g., PCIe, UCIe, CXL, Ethernet, or advanced SerDes).
• Design Skills: Proficiency in SystemVerilog, Verilog, and industry-standard EDA simulation/synthesis flows.
• Verification Skills: Deep understanding of modern verification methodologies (UVM/OVM), constrained random testing, formal verification, and coverage analysis.
• Startup Mindset: Highly adaptable, proactive problem-solver with a proven track record of delivering results in a dynamic, fast-moving environment.

Compensation:

• Salary commensurate with experience
• Performance incentives
• Equity