Senior Director, High-Speed IO Architecture & Design

Advanced Micro Devices, Inc.; Santa Clara (CA); Sur place; USD 180 000 - 320 000; Plein temps

Résumé du poste

Advanced Micro Devices, Inc. is seeking an experienced leader to head the hardware/digital IP design engineering team in Santa Clara, CA.

You will drive multi-product IP development, oversee System, Digital, RTL/logic design, and collaborate across IP, Sub-System, and SoC teams to translate requirements into implementable plans. The role demands a strong track record in high-speed IO IPs, architecture decisions, and effective mentoring of distributed engineers.

Qualifications

• Master’s degree or PhD in Electrical Engineering or related field.
• Strong leadership and mentoring of distributed engineering teams.
• Experience delivering high-speed IO IPs in CMOS nodes and production tape-outs.
• Excellent written and verbal communication and cross-functional collaboration.

Responsabilités

• Provide technical leadership for the hardware/digital semiconductor design organization.
• Lead and manage a team of System, Digital hardware, front-end/RTL/logic designers.
• Plan and track design work, priorities, schedules, and staffing; hire as needed.
• Collaborate with IP, Sub-System, and SoC architects to translate requirements into microarchitecture and plans.
• Drive IP architecture/microarchitecture, circuit architecture, and digital subsystem blocks.

Connaissances

High-Speed IO

IP leadership

People management

Digital design

Cross-functional collab

Tape-out experience

RTL/logic design

Architecture reviews

Formation

MS/PhD in EE

Outils

GDSII

EDA tools

Verilog/SystemVerilog

Description du poste

Advanced Micro Devices, Inc. is seeking an experienced leader to head the hardware/digital IP design engineering team in Santa Clara, CA.

You will drive multi-product IP development, oversee System, Digital, RTL/logic design, and collaborate across IP, Sub-System, and SoC teams to translate requirements into implementable plans. The role demands a strong track record in high-speed IO IPs, architecture decisions, and effective mentoring of distributed engineers.