GPU Pipeline RTL Designer — Microarchitecture & PPA

Oxmiq Labs; Campbell (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A leading technology company in California seeks a Mid-Senior level engineer to take ownership of microarchitecture and RTL design for GPU pipeline blocks. The role involves defining pipeline stages, implementing SystemVerilog for PPA optimizations, and collaborating closely with the architecture team to deliver high-performance GPUs. Ideal candidates will have 5+ years of experience and comprehensive knowledge of GPU architecture.

Qualifications

• 5+ years industry experience on desktop, mobile, or data center GPUs.
• Proficient in RTL design and PPA optimization.
• Strong understanding of GPU architecture and micro-architecture.

Responsibilities

• Define pipeline stages and write design specs.
• Implement clean, synthesizable SystemVerilog for performance optimization.
• Collaborate with architecture team on requirements and performance targets.

Skills

RTL design (SystemVerilog)

PPA optimization

Team collaboration

Understanding of GPU architecture

Unit tests and verification

Tools

VCS/Questa

Verdi

Jasper/IFV

DC/Genus

PrimeTime/Tempus

Job description

A leading technology company in California seeks a Mid-Senior level engineer to take ownership of microarchitecture and RTL design for GPU pipeline blocks. The role involves defining pipeline stages, implementing SystemVerilog for PPA optimizations, and collaborating closely with the architecture team to deliver high-performance GPUs. Ideal candidates will have 5+ years of experience and comprehensive knowledge of GPU architecture.