ASIC Design Engineer: RTL & Microarchitecture, Equity

NVIDIA Corporation; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in Santa Clara, CA, seeks an ASIC Design Engineer to develop high-performance RTL for SoC and GPU products. You will draft microarchitecture, implement RTL in Verilog, and collaborate with architects and verification teams to deliver verified builds.

The role requires 2+ years of RTL experience, strong micro-architecture skills, and proficiency in Verilog, Python, and Perl. Equity and benefits accompany the base compensation, with a salary range disclosed for Levels 2 and 3.

Qualifications

• BS/MS Degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science.
• 2+ years of RTL design experience.
• Strong in micro-architecture and RTL development (Verilog) and front-end flows including logic synthesis, power, and timing analysis.
• Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.
• Excellent interpersonal skills and a proven ability to work well in a team.

Responsibilities

• Drafting microarchitecture documents and implementing high-performance, area- and power-efficient RTL to meet defined targets.
• Analyzing architectural trade-offs based on features, performance, and constraints.
• Crafting micro-architectures and delivering fully verified, synthesis- and timing-clean builds.

Skills

C/C++ skills

Team collaboration

Education

BS/MS Degree in EE/CE/CS

Tools

Verilog

Python

Perl

Job description

NVIDIA Corporation in Santa Clara, CA, seeks an ASIC Design Engineer to develop high-performance RTL for SoC and GPU products. You will draft microarchitecture, implement RTL in Verilog, and collaborate with architects and verification teams to deliver verified builds.

The role requires 2+ years of RTL experience, strong micro-architecture skills, and proficiency in Verilog, Python, and Perl. Equity and benefits accompany the base compensation, with a salary range disclosed for Levels 2 and 3.