Senior ASIC Clocks IP Engineer – RTL to Silicon

NVIDIA Corporation; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA Corporation in Santa Clara, CA seeks a Senior ASIC Design Engineer for Clocks IP to architect clock domains for GPUs/CPUs, collaborating with front-end, floorplanning and back-end teams to meet timing, PPA and DFT requirements.

Role involves implementing clocking topologies in RTL, evaluating trade-offs across DFx, physical implementation and power, and aiding silicon bring-up with verification teams. 3+ years in RTL design and strong Python scripting are required.

Qualifications

• BS in Electrical Engineering or equivalent experience (MS preferred).
• 3+ years of relevant work experience in ASIC/RTL design.
• Proficient in Verilog, RTL verification, and logic synthesis.
• Strong Python or scripting language skills.
• Excellent collaboration across multiple teams.

Responsibilities

• Architect clock domain to meet functional, physical and testing requirements.
• Collaborate with multiple teams to design GPUs/CPUs clocks meeting constraints.
• Improve PPA by evaluating DFx, Physical Implementation, Power and Timing trade-offs.
• Develop clocking topologies in RTL and support silicon bring-up.
• Deliver clock RTL information to verification, timing and DFT teams.

Skills

RTL design (Verilog)

Verification

Logic synthesis

Python scripting

PPA optimization

Collaboration

On-chip clocking

Noise/crosstalk/OCV awareness

Education

BS in Electrical Engineering

MS preferred

Job description

NVIDIA Corporation in Santa Clara, CA seeks a Senior ASIC Design Engineer for Clocks IP to architect clock domains for GPUs/CPUs, collaborating with front-end, floorplanning and back-end teams to meet timing, PPA and DFT requirements.

Role involves implementing clocking topologies in RTL, evaluating trade-offs across DFx, physical implementation and power, and aiding silicon bring-up with verification teams. 3+ years in RTL design and strong Python scripting are required.