GFX/Display IP Digital Design Engineer - Power-Efficient SoCs

Meta; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking a Design Engineer to advance ASIC digital design and low-power hardware solutions in Sunnyvale. You will work on state-of-the-art SoCs, map algorithms to hardware, and collaborate with DV, PD, and verification teams to ensure robust IP integration.

The role emphasizes micro-architecture, RTL coding, and design verification for complex IPs, with focus on power and area optimization and collaboration across engineering teams.

Qualifications

• Bachelor's degree or equivalent in CS/CE or related field.
• 6+ years hardware design experience for production silicon shipped in volume.
• Experience communicating design decisions to cross-functional partners such as verification, physical design, and architecture teams

Responsibilities

• Contribute to ASIC digital µArchitecture and design.
• Assist performance/power analysis of the design and help meet power and performance targets.
• Collaborate with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration.
• Work with adjacent teams such as Verification, Physical Design, and Design-for-Test.
• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads.

Skills

RTL design

Digital microarchitecture

Hardware design

C/C++

Python

Shell scripting

Verification collaboration

Power optimization

AI tool integration

Education

Bachelor's degree in CS/CE or related field

Tools

Synthesis tools

Static timing analysis

EDA workflows

Python tooling

Job description

Meta is seeking a Design Engineer to advance ASIC digital design and low-power hardware solutions in Sunnyvale. You will work on state-of-the-art SoCs, map algorithms to hardware, and collaborate with DV, PD, and verification teams to ensure robust IP integration.

The role emphasizes micro-architecture, RTL coding, and design verification for complex IPs, with focus on power and area optimization and collaboration across engineering teams.