GFX/Display IP Digital Design Engineer: RTL & SoC

Meta; Redmond (WA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking a Design Engineer to contribute to advanced hardware including ASICs and SoCs. You will design digital architectures, optimize power and performance, and map algorithms to hardware with cross-functional teams in a fast-moving research environment.

The role requires extensive RTL coding, micro-architecture work, and collaboration with DV, PD, and architecture teams to deliver production silicon.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience.
• 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume.
• Experience in digital design µArchitecture, RTL coding, and micro-architecture development.
• Ability to communicate design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams.

Responsibilities

• Contribute to ASIC digital µArchitecture and design.
• Assist performance/power analysis of the design and help meet power and performance targets.
• Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration.
• Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test.
• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads.

Skills

RTL design

Microarchitecture

Digital design

C/C++

Python

Cross-functional collaboration

Synthesis

Timing analysis

Education

Bachelor's degree in CS/CE or equivalent

Tools

Synthesis tools

Static timing analysis

Job description

Meta is seeking a Design Engineer to contribute to advanced hardware including ASICs and SoCs. You will design digital architectures, optimize power and performance, and map algorithms to hardware with cross-functional teams in a fast-moving research environment.

The role requires extensive RTL coding, micro-architecture work, and collaboration with DV, PD, and architecture teams to deliver production silicon.