Power-Driven ASIC Engineer: EDA Flows & Signoff

Meta; Austin (TX); On-site; USD 114,000 - 172,000; Full time

Benefits offered by this job

Equity

Bonus

Benefits

Job summary

Meta is seeking an ASIC Engineer specialized in power on the EDA Infrastructure team in Austin to build and optimize power analysis flows and signoff methodologies across RTL to GDSII. You will collaborate with RTL, physical design, and verification teams to reduce power hotspots and drive efficiency in custom ASIC designs.

The role involves developing scripts, evaluating EDA tools, and defining power methodology guidelines to support next-generation silicon design and verification at Meta.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.
• 6+ years of experience in ASIC design or physical design with a focus on power analysis, power optimization, or power signoff.
• Experience developing or maintaining EDA flows for power analysis using tools such as PrimePower or Voltus.
• Experience with power intent specification languages such as UPF or CPF and their application across RTL-to-GDSII flows.
• Experience scripting in Python, Tcl, or shell to build and automate EDA infrastructure workflows.
• Experience collaborating across RTL design, physical design, and verification disciplines to drive power closure on complex ASIC designs.
• Degree must be completed prior to joining Meta.

Responsibilities

• Develop and maintain power analysis flows including dynamic and static power estimation, vectorless analysis, and power intent verification using industry-standard EDA tools.
• Define and implement power methodology guidelines for RTL, synthesis, and physical design stages of the ASIC development flow.
• Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots and inefficiencies across custom ASIC designs.
• Build and optimize EDA infrastructure scripts and automation frameworks to improve power signoff accuracy and turnaround timeli>
• Evaluate and integrate commercial and internally developed EDA tools into the power analysis flow, providing technical assessments and recommendations.
• Develop power intent specifications using UPF or CPF and ensure consistent application across design and implementation stages.
• Establish power budgets and track power metrics across design milestones, communicating results and risks to cross-functional stakeholders.
• Drive continuous improvement of power closure methodologies by analyzing results across multiple tape-outs and identifying systemic opportunities.
• Provide technical guidance to other engineers on power analysis best practices, flow usage, and debug techniques.
• Partner with EDA tool vendors to evaluate new capabilities and influence tool roadmaps to meet Meta silicon design requirements

Skills

Power analysis

EDA tooling

Python scripting

Tcl scripting

Shell scripting

Power integrity

Education

Bachelor's degree in CS/CE or related field

Tools

Synopsys PrimePower

Cadence Voltus

UPF/CPF

Job description

Meta is seeking an ASIC Engineer specialized in power on the EDA Infrastructure team in Austin to build and optimize power analysis flows and signoff methodologies across RTL to GDSII. You will collaborate with RTL, physical design, and verification teams to reduce power hotspots and drive efficiency in custom ASIC designs.

The role involves developing scripts, evaluating EDA tools, and defining power methodology guidelines to support next-generation silicon design and verification at Meta.