GFX/Display IP Digital Design Engineer

Meta; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking a Design Engineer to advance ASIC digital design and low-power hardware solutions in Sunnyvale. You will work on state-of-the-art SoCs, map algorithms to hardware, and collaborate with DV, PD, and verification teams to ensure robust IP integration.

The role emphasizes micro-architecture, RTL coding, and design verification for complex IPs, with focus on power and area optimization and collaboration across engineering teams.

Qualifications

• Bachelor's degree or equivalent in CS/CE or related field.
• 6+ years hardware design experience for production silicon shipped in volume.
• Experience communicating design decisions to cross-functional partners such as verification, physical design, and architecture teams

Responsibilities

• Contribute to ASIC digital µArchitecture and design.
• Assist performance/power analysis of the design and help meet power and performance targets.
• Collaborate with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration.
• Work with adjacent teams such as Verification, Physical Design, and Design-for-Test.
• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads.

Skills

RTL design

Digital microarchitecture

Hardware design

C/C++

Python

Shell scripting

Verification collaboration

Power optimization

AI tool integration

Education

Bachelor's degree in CS/CE or related field

Tools

Synthesis tools

Static timing analysis

EDA workflows

Python tooling

Job description

Meta is seeking highly skilled Design Engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning and network acceleration. You will collaborate with researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the‑art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.

GFX/Display IP Digital Design Engineer Responsibilities:

• Contribute to ASIC digital µArchitecture and design
• Assist performance/power analysis of the design and help meet power and performance targets
• Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration
• Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test
• Develop micro-architecture, RTL coding, and design verification for complex IPs
• Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume
• Experience in digital design µArchitecture, RTL coding, and micro-architecture development
• Experience communicating technical design decisions and trade-offs to cross‑functional partners such as verification, physical design, and architecture teams

Preferred Qualifications:

• Experience micro‑architecting and designing IP with heavy fixed‑point and/or floating‑point data path logic
• Experience with synthesis, static timing analysis, and timing closure methodologies
• Experience collaborating with verification or physical design teams during the silicon development cycle
• Experience with microarchitecture and design optimization for power, performance, and area
• Experience with at least one procedural programming language (C, C++, Python, etc.)
• Experience with shell scripting (bash and/or csh)
• Experience with CDC and RDC analysis
• Experience with pixel processing pipelines like 2D/3D GFX engines and/or display processing units
• Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)
• Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)
• Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Aff…

$146,000/year to $209,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.