Senior ASIC Power Engineer — EDA & Power Flows

Meta; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta is seeking an ASIC Engineer specializing in power to join the EDA Infrastructure team in Sunnyvale. You will develop and maintain power analysis and optimization flows to help silicon engineers model, estimate, and reduce power consumption in custom ASIC designs.

You will define power methodology, collaborate with RTL and physical design teams, and drive power closure across multiple tape-outs while evaluating new EDA tools and automating workflows.

Qualifications

• Bachelor's degree in CS/CE or related field.
• 6+ years in ASIC design or physical design with power focus.
• Experience building EDA power analysis flows (PrimePower/Voltus).
• Experience with UPF/CPF in RTL-to-GDSII.
• Scripting in Python, Tcl, or shell to automate flows.
• Collaborate across RTL, physical design, and verification.

Responsibilities

• Develop and maintain power analysis flows including dynamic and static power estimation.
• Define and implement power methodology guidelines for RTL, synthesis, and physical design.
• Collaborate with RTL, physical design, and verification to resolve power hotspots.
• Build and optimize EDA automation scripts to improve power signoff turnaround.
• Evaluate and integrate EDA tools into power analysis flow.
• Develop power intent specs using UPF/CPF across design stages.
• Establish power budgets and track metrics across milestones.
• Drive continuous improvement of power closure across tape-outs.
• Provide technical guidance on power analysis best practices.

Skills

Power analysis

Power optimization

Python scripting

Cross-functional collaboration

Communication skills

Education

Bachelor's degree in CS/CE or related field

Tools

Synopsys PrimePower

Cadence Voltus

UPF/CPF

Job description

Meta is seeking an ASIC Engineer specializing in power to join the EDA Infrastructure team in Sunnyvale. You will develop and maintain power analysis and optimization flows to help silicon engineers model, estimate, and reduce power consumption in custom ASIC designs.

You will define power methodology, collaborate with RTL and physical design teams, and drive power closure across multiple tape-outs while evaluating new EDA tools and automating workflows.