GenAI-Driven Wireless SoC Mixed-Signal DV Engineer

Apple, Inc.; Sunnyvale (CA); On-site; USD 129,000 - 225,000; Full time

Benefits offered by this job

Medical & Dental

Retirement benefits

Employee stock programs

Tuition reimbursement

Relocation

Discretionary bonuses

Job summary

Apple, Inc. in Sunnyvale, CA, seeks a Mixed‑Signal Design Verification Engineer to verify RF and mixed‑signal blocks within wireless SoCs.

You will collaborate with analog/RF design, SoC DV/design, PHY DV/design, and power management DV/design, using best‑in‑class verification methodologies including GenAI to ensure silicon‑correct functionality. You’ll own an area with autonomy, build and reuse monitors and RNMs, and help improve verification flows while contributing to tape‑out readiness

Qualifications

• Minimum requirement of a bachelor's degree.
• Experience with RF/mixed-signal blocks and SoCs.
• Experience building mixed-signal testbenches, checkers and tests using SystemVerilog.
• Strong verification skills in critical thinking, problem solving, testing, and debugging.
• Solid understanding of analog/RF circuits such as PLLs, ADCs, RX/TX chains or power delivery.
• Great communicator and team collaborator; self-motivated, organized, and eager to take on diverse challenges.

Responsibilities

• Review specifications and collaborate with the design and system teams to extract features, define and execute verification plans.
• Develop top/block level digital/mixed-signal (DMS) testbenches, tests and sequences.
• Build and reuse monitors and checkers for RF/mixed-signal blocks.
• Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage.
• Build SystemVerilog behavioral and real-number models (RNM) of RF and analog blocks (RX, TX, ADC, PLL, power management or clock distribution) and validate them against the schematic design.
• Create and improve verification flows and automation, including leveraging GenAI.
• Improve our mixed-signal verification methodology with novel ideas.

Skills

RF blocks

SystemVerilog

Debugging

Problem solving

Team collaboration

Communication

Education

Bachelor's degree

Tools

UVM

UPF

Python

Matlab

Virtuoso Composer

ADE

HED

Job description

Apple, Inc. in Sunnyvale, CA, seeks a Mixed‑Signal Design Verification Engineer to verify RF and mixed‑signal blocks within wireless SoCs.

You will collaborate with analog/RF design, SoC DV/design, PHY DV/design, and power management DV/design, using best‑in‑class verification methodologies including GenAI to ensure silicon‑correct functionality. You’ll own an area with autonomy, build and reuse monitors and RNMs, and help improve verification flows while contributing to tape‑out readiness