Wireless Mixed-Signal Verification Engineer

Apple Inc.; San Diego (CA); Presencial; USD 123.000 - 214.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical & dental coverage

Retirement benefits

Product discounts

Educational reimbursement

Relocation eligibility

Descripción de la vacante

Apple Inc. in San Diego is seeking a Mixed Signal Design Verification Engineer to join the wireless silicon group.

You will verify RF and mixed-signal blocks within the wireless SoC and collaborate with analog/RF, digital DV, and system teams to ensure silicon-correct functionality and timely tape-out. Responsibilities include building top-level testbenches in UVM, debugging, automation scripts, and advancing verification methodologies, including the use of AI, to meet aggressive project

Formación

• Bachelor's degree required in a technical field.
• Experience verifying RF/Mixed-Signal blocks in SOCs.
• Expertise building Mixed-Signal testbenches with SystemVerilog.
• Experience with UVM and HDL (SystemVerilog/Verilog).
• Strong debugging and problem-solving skills.
• Knowledge of analog/RF blocks.
• Experience with Python or Matlab.
• Experience with Virtuoso Composer, ADE, and HED.

Responsabilidades

• Review specifications, extract features, define verification plan.
• Develop Mixed Signal and Digital testbenches in UVM framework.
• Build monitors and checkers for RF/Mixed-Signal blocks.
• Debug failures, fix testbench/model issues, manage bugs and coverage.
• Write scripts for automation of flow.
• Improve verification methodology with AI ideas.

Conocimientos

SystemVerilog

UVM

Python

Matlab

Debugging

Analog/RF blocks knowledge

Educación

Bachelor's degree

Herramientas

Virtuoso Composer

ADE

HED

Descripción del empleo

Apple Inc. in San Diego is seeking a Mixed Signal Design Verification Engineer to join the wireless silicon group.

You will verify RF and mixed-signal blocks within the wireless SoC and collaborate with analog/RF, digital DV, and system teams to ensure silicon-correct functionality and timely tape-out. Responsibilities include building top-level testbenches in UVM, debugging, automation scripts, and advancing verification methodologies, including the use of AI, to meet aggressive project