ASIC Implementation Engineer, Static Verification

Meta

Sunnyvale (CA)

On-site

USD 146,000 - 209,000

Full time

22 hours ago
Be an early applicant
Application generator

Turn this role into an interview — a resume and cover letter built around what this employer wants.

Get past ATS filters

Benefits offered by this job

Equity
Bonus
Benefits

Job summary

Meta is hiring ASIC Frontend Implementation Engineers in Sunnyvale, CA. The role focuses on RTL-to-netlist implementation for data center SoCs and IP, including Lint, CDC analysis, timing constraints, and synthesis.

You’ll work with Design, DV, Emulation, and Physical Design teams to optimize timing, area, and power. Qualified candidates have a strong background in SystemVerilog HDL, front-end flows, and experience with Design Compiler, Spyglass, or PrimeTime.

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering or equivalent practical experience.
  • 6+ years of experience in static verification tools including RTL Lint and CDC analysis.
  • Experience with SOC CDC signoff and front-end ASIC flows.

Responsibilities

  • Perform clock domain crossing analyses and sign-off for CDC several designs.
  • Perform reset domain crossing checks and collaborate with design and FW teams.
  • Perform RTL lint and work with designers to create waivers.
  • Perform RTL DFT analysis and improve scan coverage for stuck-at faults.
  • Run logic/physical synthesis to generate optimized gate-level netlists.
  • Develop automation scripts and methodologies for FE-tools (Lint, CDC, RDC).
  • Collaborate with design, DV, emulation, and physical design teams for handoff and timing feedback.

Skills

Static verification tools
RTL Lint
CDC analysis
Scripting (Perl/Python/TCL)

Education

Bachelor's degree in CS/CE or equivalent

Tools

Design Compiler
Spyglass
PrimeTime
Make

Job description

Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications.

ASIC Implementation Engineer, Static Verification Responsibilities:
  • Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC
  • Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC
  • Perform RTL Lint and work with the Designers to create waivers
  • Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults
  • Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
  • Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,)
  • Work closely with the Design Engineers, DV Engineers, and Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback
Minimum Qualifications:
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • Currently has a Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
  • 6+ years of experience in static verification tools
  • Experience with Lint, Clock Domain and Reset Domain crossing
  • Experience with SOC CDC signoff
  • Knowledge of SOC integration (clocking, reset, PLL, etc.)
  • Knowledge of front-end ASIC flows
  • Experience with RTL design using SystemVerilog or other HDL
  • Experience with communicating across functional internal teams and vendors
Preferred Qualifications:
  • Experience with Netlist-CDC Analysis and improving MTBF
  • Experience with SOC Design Integration and Front-End Implementation
  • Scripting and programming experience using Perl/Python, TCL, and Make
  • Experience with developing structural rule based checks for RTL & Netlist
  • Experience with Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools
  • Knowledge of Timing/physical libraries, SRAM Memories
About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Aff… We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.

$146,000/year to $209,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

ASIC Implementation Engineer - Static Verification
ASIC Implementation Engineer - Static Verification

Meta • Sunnyvale (CA)

On-site
USD 114,000 - 172,000
ASIC Engineer, Implementation - Timing
ASIC Engineer, Implementation - Timing

Meta • Austin (TX)

On-site
USD 114,000 - 172,000
Bonus
Equity
Benefits
ASIC Engineer, Implementation - Timing
ASIC Engineer, Implementation - Timing

Meta • Sunnyvale (CA)

On-site
USD 114,000 - 172,000
Bonus
Equity
Benefits
ASIC Engineer, Design
ASIC Engineer, Design

Meta • Austin (TX)

On-site
USD 178,000 - 250,000
Bonus
Equity
Benefits
ASIC Engineer, EDA Infrastructure
ASIC Engineer, EDA Infrastructure

Meta • Menlo Park (CA)

On-site
USD 114,000 - 172,000
ASIC Engineer, Implementation - Timing
ASIC Engineer, Implementation - Timing

Meta Careers • Austin (TX)

On-site
USD 114,000 - 172,000
Silicon Engineer
Silicon Engineer

Meta • Sunnyvale (CA)

On-site
USD 114,000 - 172,000
Bonus
Equity
Benefits
Silicon Engineer
Silicon Engineer

Meta • Austin (TX)

On-site
USD 114,000 - 172,000
Technical Lead, Infrastructure Silicon Validation
Technical Lead, Infrastructure Silicon Validation

Meta • Sunnyvale (CA)

On-site
USD 212,000 - 294,000
Bonus
Equity
Benefits
ASIC Engineer, Power Management Design Verification
ASIC Engineer, Power Management Design Verification

Meta • Sunnyvale (CA)

On-site
USD 178,000 - 250,000