FPGA Verification Engineer (SystemVerilog & UVM)

Compunnel Inc.; Mountain View (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

Compunnel Inc. in Mountain View, California, is seeking an FPGA Verification Engineer to verify FPGA designs using SystemVerilog and UVM, employing debugging and coverage analysis to ensure high-quality deliverables.

You will collaborate with cross-functional teams to address design issues and optimize verification flows. Applicants should have FPGA verification experience, strong scripting with Python or Perl, and familiarity with VHDL/Verilog.

Qualifications

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience in FPGA verification.
• Proficiency with scripting languages such as Python or Perl.
• Familiarity with hardware description languages including VHDL and Verilog.

Responsibilities

• Apply strong understanding of FPGA design principles and architectures to support verification activities.
• Utilize SystemVerilog and UVM methodology for FPGA verification.
• Use industry-standard verification tools such as QuestaSim and Synopsys VCS.
• Perform code coverage and functional coverage analysis.
• Debug and resolve issues efficiently.
• Work collaboratively with engineering teams and communicate technical findings effectively.

Skills

SystemVerilog

UVM

Debugging

Coverage analysis

Python

Perl

VHDL

Verilog

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Master’s degree (beneficial)

Tools

QuestaSim

Synopsys VCS

Job description

Compunnel Inc. in Mountain View, California, is seeking an FPGA Verification Engineer to verify FPGA designs using SystemVerilog and UVM, employing debugging and coverage analysis to ensure high-quality deliverables.

You will collaborate with cross-functional teams to address design issues and optimize verification flows. Applicants should have FPGA verification experience, strong scripting with Python or Perl, and familiarity with VHDL/Verilog.