On-Site FPGA Verification Engineer with UVM/SystemVerilog

STI; Santa Clara (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

STI in Santa Clara, CA is seeking an experienced FPGA Verification Engineer to verify complex FPGA designs, ensuring functionality, performance, and reliability. You will collaborate with design teams to develop verification plans and execute them end-to-end.

You will build and maintain SystemVerilog/UVM test benches, run simulations with QuestaSim or Synopsys VCS, perform coverage analysis, debug issues, and document results.

Qualifications

• Requires 3+ years of FPGA verification experience.
• Strong experience with SystemVerilog and UVM for verification.
• Familiarity with coverage analysis and debugging complex FPGA designs.

Responsibilities

• Develop and execute verification plans for FPGA designs.
• Create and maintain verification test benches using UVM and SystemVerilog.
• Write and debug test cases covering functionality and edge cases.
• Perform code and functional coverage analysis.
• Identify and debug issues with design engineers.
• Document verification results and reports.
• Participate in design reviews and contribute to verification strategy.
• Stay up-to-date with verification methodologies and tools.

Skills

FPGA

SystemVerilog

UVM

QuestaSim

Synopsys VCS

Code Coverage

Functional Coverage

Debugging

Communication

Collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

QuestaSim

Synopsys VCS

Job description

STI in Santa Clara, CA is seeking an experienced FPGA Verification Engineer to verify complex FPGA designs, ensuring functionality, performance, and reliability. You will collaborate with design teams to develop verification plans and execute them end-to-end.

You will build and maintain SystemVerilog/UVM test benches, run simulations with QuestaSim or Synopsys VCS, perform coverage analysis, debug issues, and document results.