FPGA Verification Engineer at Unicom Technologies Inc.

Allps GmbH; Santa Clara (CA); Sur place; USD 124 000 - 176 000; Plein temps

Résumé du poste

A leading engineering company is seeking a highly skilled FPGA Verification Engineer in Santa Clara, CA. You will verify complex FPGA designs, collaborating closely with design engineers and ensuring product quality. The ideal candidate will have over 8 years of experience in FPGA and strong proficiency in UVM and SystemVerilog. This is a full-time onsite role, requiring a Bachelor's or Master's degree in Electrical or Computer Engineering. Competitive rate offered with 5 days onsite per week.

Qualifications

• 8+ years in FPGA design.
• 5+ years of experience in UVM.
• 5+ years of experience in SystemVerilog.
• 3+ years of experience in FPGA verification.

Responsabilités

• Develop and execute verification plans for FPGA designs.
• Create and maintain test benches using UVM and SystemVerilog.
• Document verification results and provide reports.
• Participate in design reviews and contribute to verification strategy.

Connaissances

FPGA

UVM

SystemVerilog

Debugging

Collaboration

Formation

Bachelor's degree in Electrical Engineering

Master's degree in a related field

Outils

QuestaSim

Synopsys VCS

Description du poste

Location – Santa Clara, CA
Onsite Requirement -Yes
Number of days onsite – 5 Days

Rate:$72/Hr On C2C

Must Have Skills – FPGA Verification Engineer
Skill 1 – 8+ Years in FPGA
Skill 2 – 5+ Years of Exp in UVM
Skill 2 – 5+ Years of Exp in System Verilog

Job Description:

We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our products.

Key Responsibilities:

• Develop and execute comprehensive verification plans for FPGA designs.
• Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, SystemVerilog).
• Write and debug test cases to verify functionality, performance, and corner cases.
• Perform code coverage and functional coverage analysis.
• Identify and debug issues, working closely with design engineers to resolve them.
• Document verification results and provide clear and concise reports.
• Participate in design reviews and contribute to the overall verification strategy.
• Stay up-to-date with the latest verification methodologies and tools.

Skills Required:

• Strong understanding of FPGA design principles and architectures.
• Proficiency in SystemVerilog and UVM verification methodology.
• Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).
• Knowledge of code coverage and functional coverage analysis.
• Excellent debugging and problem-solving skills.
• Strong communication and collaboration skills.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in FPGA verification.
• Experience with scripting languages (e.g., Python, Perl).
• Familiarity with hardware description languages (e.g., VHDL, Verilog).