FPGA Verification Engineer II — Space-Grade UVM & CI Expert

CesiumAstro; Austin (TX); On-site; USD 113,000 - 136,000; Full time

Benefits offered by this job

Stock options

Health benefits

Retirement plan

Job summary

CesiumAstro is hiring an FPGA Verification Engineer II in Austin, TX. You will contribute to FPGA/digital design verification, CI/regression testing, and reusable VIP modules. The role involves mentoring engineers and collaborating with senior leadership on modern verification approaches.

You will work with MATLAB/Python models and DPI-C integrations, focusing on scalable testbenches and continual process improvements within a dynamic space tech environment.

Qualifications

• BS or MS degree in CS/EE/CE.
• 2+ years of verification/automation experience.
• FPGA/digital design verification techniques knowledge.

Responsibilities

• Evaluate and implement FPGA/digital design verification, simulation and emulation infrastructure.
• Develop CI/regression testing infrastructure and automation.
• Build UVMf top-level and module testbenches with DPI-C integration to MATLAB/Python models.
• Lead development of reusable VIP modules.
• Mentor engineers on UVMf testbenches and FPGA/digital design approaches.
• Assist in evaluating processes for Xilinx TLM models and QEMU-RP integration.
• Collaborate with vendors to define future model deliverables.
• Stay updated on FPGA/digital design industry best practices.
• Work with leadership to implement process improvements non-disruptively.

Skills

VHDL

Verilog

SystemVerilog

C/C++

SystemC

UVM/UVMf

DPI-C

QEMU

VIP

Linux

Education

BS or MS in Computer Science, Electrical Engineering, or Computer Engineering

Tools

Xilinx tools

Job description

CesiumAstro is hiring an FPGA Verification Engineer II in Austin, TX. You will contribute to FPGA/digital design verification, CI/regression testing, and reusable VIP modules. The role involves mentoring engineers and collaborating with senior leadership on modern verification approaches.

You will work with MATLAB/Python models and DPI-C integrations, focusing on scalable testbenches and continual process improvements within a dynamic space tech environment.