FPGA Verification Engineer II – Space-Grade, UVM Expert

Woven; Westminster, Northern (CO, KY); Hybrid; USD 113,000 - 136,000; Full time

Job summary

CesiumAstro is seeking an FPGA Verification Engineer II to advance verification and validation for our space-focused FPGA/digital design efforts. You will contribute to simulation, testbench development, and CI/automation while mentoring teammates on modern verification techniques.

You will collaborate with senior leaders to integrate DPI-C dataplane verification with MATLAB/Python models and drive reusable VIP module development.

Qualifications

• BS or MS in CS, EE, or CE.
• Minimum 2 years of verification/automation experience.
• Knowledge of FPGA verification techniques including VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional analysis, QEMU and VIP.
• Understanding of CI, regression testing and HIL testing.
• Competency with Linux.
• Knowledge of vendor-provided FPGA development tools with a focus on Xilinx tools.

Responsibilities

• Contribute to evaluation and implementation of FPGA and digital design simulation, verification and emulation infrastructure.
• Develop CI and regression testing infrastructure.
• Develop UVMf-based testbenches and DPI-C integration with MATLAB/Python models.
• Lead development of reusable VIP modules.
• Mentor engineers on UVMf testbench usage and FPGA design approaches.
• Assist in evaluating current processes with VHDL/Verilog models and QEMU-RP integration.
• Collaborate with vendors to define future model deliverables.
• Maintain up-to-date knowledge of FPGA/digital design best practices.
• Work with leadership to implement process improvements.

Skills

FPGA verification

UVM/UVMf

CI/Regression

VHDL/Verilog

DPI-C integration

Python

MATLAB

C/C++

VIP modules

Education

BS or MS in CS/EE/CE

Tools

Xilinx tools

QEMU

Job description

CesiumAstro is seeking an FPGA Verification Engineer II to advance verification and validation for our space-focused FPGA/digital design efforts. You will contribute to simulation, testbench development, and CI/automation while mentoring teammates on modern verification techniques.

You will collaborate with senior leaders to integrate DPI-C dataplane verification with MATLAB/Python models and drive reusable VIP module development.