FPGA Software Engineer I - Timing & Power Modeling

Microchip Technology Inc.; San Jose (CA); Presencial; USD 70.000 - 143.000; Jornada completa

Descripción de la vacante

Microchip Technology Inc. in San Jose, CA, seeks an FPGA Software Engineer to join the Timing, Power, and Modeling group. You will help design and maintain timing analysis and performance modeling tools used across FPGA design flows.

This role focuses on C++, data structures, and scripting with Python/Bash/TCL, with opportunities to contribute to modeling, optimization, and exploration of new FPGA architectures. The team emphasizes collaboration and growth.

Formación

• Bachelor's degree in Computer Science, Electrical Engineering, or Computer Engineering.
• 0-3 years of related field experience.
• Strong knowledge in C++ and data structures.
• Experience with shell scripting (Python, Bash, TCL).

Responsabilidades

• Design, develop, test, debug, and maintain static timing analysis software.
• Modeling complex digital components, including high-speed IOs.
• Developing solutions tailored towards supporting very large graph representation.
• Optimizing architecture processing and analysis in terms of run-time and memory footprint.
• Integrate capabilities in an internal flow to evaluate future FPGA architectures.
• Participate to the R&D exploration activities on topics like OCV, SSTA, IR Drop.
• Help with the enforcement of Microchip’s Software Development Processes.
• Perform design reviews, unit testing, and code reviews.
• Own and sustain product features and provide customer support.
• Continue learning latest EDA discoveries and contribute to team discussions

Conocimientos

C++ programming

Data structures & algorithms

Shell scripting (Python, Bash, TCL)

Analytical thinking

Cross-functional collaboration

Educación

Bachelor's degree in CS/EE/CE

Master's degree

Herramientas

Git

Jira

Bitbucket

TBB

Descripción del empleo

Microchip Technology Inc. in San Jose, CA, seeks an FPGA Software Engineer to join the Timing, Power, and Modeling group. You will help design and maintain timing analysis and performance modeling tools used across FPGA design flows.

This role focuses on C++, data structures, and scripting with Python/Bash/TCL, with opportunities to contribute to modeling, optimization, and exploration of new FPGA architectures. The team emphasizes collaboration and growth.