Full-Chip Timing Design & Modeling Engineer

Altera; San Jose (CA); On-site; USD 133,000 - 193,000; Full time

Job summary

Altera is seeking a Full Chip Timing Modeling and Integration Engineer to develop timing methodologies and perform full-chip timing for next-generation FPGA products. You will collaborate with cross-functional teams to define timing modeling strategies, generate high-level timing models, and validate timing models across multi-site teams.

The role requires hands-on STA experience, design automation scripting in Python and Tcl, and deep knowledge of LVF/POCV concepts, timing constraints, and

Qualifications

• Bachelor’s or Master’s in Electrical/Computer Engineering, Computer Science or related field with 5+ years in SoC development.
• 5+ years of experience with advanced semiconductor process nodes.
• 5+ years of experience with timing formats and design constraints including Liberty, Verilog and SDC.
• 5+ years of experience with Static Timing Analysis (STA) and correlating STA results with SPICE.
• 5+ years of experience in timing modeling and library QA.
• 5+ years of experience writing Python and Tcl scripts for design automation.
• 5+ years of experience applying silicon modeling concepts such as LVF and POCV.

Responsibilities

• Develop timing methodologies and execute full-chip timing for next-generation FPGA products using advanced process technologies.
• Collaborate with cross-functional teams to define timing modeling strategies and solutions.
• Generate high-level timing models and perform timing model integration and validation.
• Perform hands-on full-chip timing analysis, including clocking and timing constraint development.
• Work with Front-End and Back-End design teams to understand design architecture and implementation.
• Analyze extraction issues, design margins, timing signoff requirements, and timing quality checks.
• Debug and troubleshoot a wide variety of technical issues, including difficult and critical design issues, and proactively intervene to resolve them.
• Drive continuous improvement, efficiently solve technical issues, and communicate trade-offs across teams.
• Work independently and collaboratively to deliver high-quality results within aggressive project schedules.

Skills

Timing analysis

STA/SDC

Python scripting

Tcl scripting

Verilog

LVF/POCV concepts

Education

Bachelor’s or Master’s in EE/CE/CS

Job description

Altera is seeking a Full Chip Timing Modeling and Integration Engineer to develop timing methodologies and perform full-chip timing for next-generation FPGA products. You will collaborate with cross-functional teams to define timing modeling strategies, generate high-level timing models, and validate timing models across multi-site teams.

The role requires hands-on STA experience, design automation scripting in Python and Tcl, and deep knowledge of LVF/POCV concepts, timing constraints, and