Senior Full-Chip Timing Engineer: Modeling & Integration

191 Altera Corporation; San Jose (CA); On-site; USD 133,000 - 193,000; Full time

Job summary

Altera seeks a Full Chip Timing Modeling and Integration Engineer to develop timing methodologies and execute full-chip timing for next-generation FPGA products. You will work with cross-functional teams to define timing strategies, generate high-level models, and ensure timing model integration and validation.

The role emphasizes hands-on STA, design constraint development, and ongoing process improvements within a fast-paced, multi-site environment in San Jose, CA.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field plus 5+ years industry experience.
• Experience with advanced semiconductor process nodes (5+ years).
• Experience with timing formats and design constraints (Liberty/Verilog/SDC) (5+ years).
• 5+ years of Static Timing Analysis (STA) with SPICE correlation.
• 5+ years in timing modeling and library QA.
• 5+ years writing Python and Tcl scripts for design automation.

Responsibilities

• Develop timing methodologies and execute full-chip timing for next-generation FPGA products using advanced process technologies.
• Collaborate with cross-functional teams to define timing modeling strategies and solutions.
• Generate high-level timing models and perform timing model integration and validation.
• Perform hands-on full-chip timing analysis, including clocking and timing constraint development.
• Work with Front-End and Back-End design teams to understand design architecture and implementation.
• Analyze extraction issues, design margins, timing signoff requirements, and timing quality checks.
• Debug and troubleshoot a wide variety of technical issues, including difficult and critical design issues.
• Drive continuous improvement, efficiently solve technical issues, and communicate trade-offs across teams.
• Work independently and collaboratively to deliver high-quality results within aggressive project schedules.

Skills

Timing methodologies

Full-chip timing

Python scripting

Tcl scripting

STA

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Tools

Liberty

Verilog

Synopsys Design Constraints (SDC)

Job description

Altera seeks a Full Chip Timing Modeling and Integration Engineer to develop timing methodologies and execute full-chip timing for next-generation FPGA products. You will work with cross-functional teams to define timing strategies, generate high-level models, and ensure timing model integration and validation.

The role emphasizes hands-on STA, design constraint development, and ongoing process improvements within a fast-paced, multi-site environment in San Jose, CA.