Digital ASIC Design Engineer II: Power, Timing, & IP

Microchip Technology Inc; San Jose (CA); On-site; USD 70,000 - 143,000; Full time

Benefits offered by this job

Health benefits from day one

Retirement savings plan

ESPP with 2-year lookback

Job summary

Microchip Technology Inc is seeking an experienced ASIC/FPGA digital design engineer in the US to implement RTL (SystemVerilog) for complex digital IP blocks, driving PPA trade-offs and collaborating with SoC teams to ensure connectivity and timing targets.

You will lead lint/CDC/RDC and formal verification, work with Physical Design to close timing, and document design activities while applying scripting to improve efficiency and bring-up experiences with test equipment.

Qualifications

• BS degree in Electrical Engineering.
• 2.5 - 5 years of proven experience in ASIC or FPGA digital design.
• Proficiency in System Verilog and a deep understanding of synchronous/asynchronous design techniques.
• Experience with the full Cadence/Synopsys front-end EDA flow (e.g., VCS, SpyGlass, Design Compiler, PrimeTime).
• Familiarity with PHY or Serdes protocols, knowledge of IEEE 802.3 is a plus.
• Skillful in scripts to aid efficiency.
• Post-silicon validation or bring-up experience. Proficient in lab equipment (e.g., oscilloscope, logic analyzer, ..., etc.)

Responsibilities

• Follow the micro-architecture and implement RTL (System Verilog) of complex digital IP blocks from concept to delivery.
• Drive Power, Performance, and Area trade-offs and optimizations to meet aggressive product targets.
• Collaborate with SoC integration teams to ensure seamless connectivity and address top-level timing/congestion issues.
• Lead Lint, CDC, RDC, and formal verification efforts. Work closely with Physical Design teams to close timing and resolve routing bottlenecks.
• Cooperate with teams to verify and validate module and system functions.
• Organize documents to record design activities.

Skills

SystemVerilog

ASIC/FPGA design

Scripting

PHY/Serdes

Post-silicon validation

Education

BS in Electrical Engineering

Tools

VCS

SpyGlass

Design Compiler

PrimeTime

Job description

Microchip Technology Inc is seeking an experienced ASIC/FPGA digital design engineer in the US to implement RTL (SystemVerilog) for complex digital IP blocks, driving PPA trade-offs and collaborating with SoC teams to ensure connectivity and timing targets.

You will lead lint/CDC/RDC and formal verification, work with Physical Design to close timing, and document design activities while applying scripting to improve efficiency and bring-up experiences with test equipment.