FPGA Full-Chip Timing Architect

Altera Corp.; San Jose (CA); On-site; USD 133,000 - 193,000; Full time

Job summary

Altera Corp. in San Jose, California, seeks a Full Chip Timing Modeling and Integration Engineer to develop timing methodologies and execute full-chip timing for next-generation FPGA products using advanced process technologies.

You will collaborate with cross-functional teams to define timing modeling strategies, generate high-level timing models, and perform timing model integration and validation while meeting aggressive schedules in a fast-paced environment.

Qualifications

• Bachelor’s or Master’s degree in a related field.
• 5+ years of SoC development experience.
• 5+ years with advanced semiconductor process nodes.
• 5+ years with timing formats and design constraints (Liberty, Verilog, SDC).
• 5+ years of Static Timing Analysis (STA).
• 5+ years of timing modeling and library QA.
• 5+ years of Python and Tcl scripting.
• 5+ years of silicon modeling concepts (LVF, POCV).

Responsibilities

• Develop timing methodologies and execute full-chip timing for next-generation FPGA products.
• Collaborate with cross-functional teams to define timing modeling strategies and solutions.
• Generate high-level timing models and perform timing model integration and validation.
• Perform hands-on full-chip timing analysis including clocking and timing constraint development.
• Work with Front-End and Back-End design teams to understand design architecture.
• Analyze extraction issues, design margins, timing signoff requirements, and timing quality checks.
• Debug and troubleshoot a wide variety of technical issues and drive resolution.
• Drive continuous improvement and communicate trade-offs across teams.
• Deliver high-quality results within aggressive project schedules.

Skills

Timing analysis

Python scripting

Tcl scripting

Static Timing Analysis

Verilog

Design constraints

Cross-functional collab

Silicon modeling

AI/ML usage

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Tools

SDC

Liberty

SPICE

Job description

Altera Corp. in San Jose, California, seeks a Full Chip Timing Modeling and Integration Engineer to develop timing methodologies and execute full-chip timing for next-generation FPGA products using advanced process technologies.

You will collaborate with cross-functional teams to define timing modeling strategies, generate high-level timing models, and perform timing model integration and validation while meeting aggressive schedules in a fast-paced environment.