FPGA Silicon Validation Tech Lead: Bring-Up & Strategy

Lattice Semiconductor; San Jose (CA); On-site; USD 150,000 - 180,000; Full time

Benefits offered by this job

Competitive compensation

Equity

Benefits

High-ownership culture

Job summary

Lattice Semiconductor is searching for a Technical Leader in San Jose to own the validation strategy for next-generation FPGA silicon. This role demands in-depth experience and the ability to guide a team through successful silicon brings-up, characterization, and release.

The ideal candidate will possess over 8 years of validation experience, expertise in high-speed interfaces, and the capabilities to communicate effectively with cross-functional teams. Competitive compensation and benefits are offered in this full-time onsite position.

Qualifications

• 8+ years in post-silicon or silicon design validation.
• Proven tech lead experience, guiding a team.

Responsibilities

• Lead validation strategy for FPGA IPs.
• Drive new silicon bring-up end-to-end.
• Author test logic RTL and automation frameworks.

Skills

High-speed interface characterization

Signal integrity

FPGA development tools

Test automation in Python

Proficiency in Verilog/VHDL

Statistical analysis

Communication skills

Education

Degree in Electrical Engineering or related field

Tools

BERT

VNA

Oscilloscopes

Job description

Lattice Semiconductor is searching for a Technical Leader in San Jose to own the validation strategy for next-generation FPGA silicon. This role demands in-depth experience and the ability to guide a team through successful silicon brings-up, characterization, and release.

The ideal candidate will possess over 8 years of validation experience, expertise in high-speed interfaces, and the capabilities to communicate effectively with cross-functional teams. Competitive compensation and benefits are offered in this full-time onsite position.